PCF2127AT/1,518 NXP Semiconductors, PCF2127AT/1,518 Datasheet - Page 55

• Manufacturer Part Number: PCF2127AT/1,518
• Description: IC RTC/CALENDAR TCXO QTZ 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2127AT/1,518

• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Time Format: HH:MM:SS (12/24 hr)
• Memory Size: 512B
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Serial Clock, Timestamp, Timekeeper, Watchdog, Alarm, Calendar, Timer, Timer Interrupt
• Rtc Memory Size: 512 bytes
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 2600 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCF2127A_2
Product data sheet
9.1.1 Data transmission
9.1 SPI-bus interface
Data transfer to and from the device is made via a 3 wire SPI-bus (see
lines for input and output are split. The data input and output line can be connected
together to facilitate a bidirectional data bus (see
whenever the chip enable line pin SDA/CE is inactive.
Table 57.
[1]
The chip enable signal is used to identify the transmitted data. Each data transfer is a
byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE. The first
byte transmitted is the command byte. Subsequent bytes will be either data to be written
or data to be read (see
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W bit defines if the following
bytes will be read or write information.
Symbol
SDA/CE
SCL
SDI
SDO
Fig 34. SDI, SDO configurations
Fig 35. Data transfer overview
The chip enable must not be wired permanently LOW.
Serial interface
data bus
SDA/CE
Function
chip enable input;
active LOW
serial clock input
serial data input
serial data output
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 02 — 7 May 2010
COMMAND
35).
two wire mode
SDO
SDI
DATA
[1]
Description
when HIGH, the interface is reset;
when SDA/CE is HIGH, input may float;
when SDA/CE is HIGH, input may float;
push-pull output;
input may be higher than V
input may be higher than V
input may be higher than V
input data is sampled on the rising edge of SCL
drives from V
output data is changed on the falling edge of SCL
Integrated RTC, TCXO and quartz crystal
single wire mode
SDO
SDI
DATA
Figure
001aai560
34). The SPI-bus is initialized
SS
to V
BBS
DATA
;
PCF2127A
DD
DD
DD
Table
© NXP B.V. 2010. All rights reserved.
;
013aaa311
57). The data
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