ISL12022IBZ-T7A Intersil, ISL12022IBZ-T7A Datasheet - Page 14

• Manufacturer Part Number: ISL12022IBZ-T7A
• Description: IC RTC/CALENDAR TEMP SNSR 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022IBZ-T7A

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Example - When the LBAT85 is Set To “1” In Battery Mode:
The minute the register changes to 19h when the device is in
battery mode, the LBAT85 is set to “1” the next time the
device switches back to Normal Mode.
Example - When the LBAT85 Remains at “0” In Battery
Mode:
If the device enters into battery mode after the minute
register reaches 20h and switches back to Normal Mode
before the minute register reaches 29h, then the LBAT85 bit
will remain at “0” the next time the device switches back to
Normal Mode.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
In Normal Mode (V
level has dropped below the pre-selected trip levels. The trip
points are selected by three bits: VB75Tp2, VB75Tp1 and
VB75Tp0 in the PWR_VBAT registers. The LBAT75
detection happens automatically once every minute when
seconds register reaches 59. The detection can also be
manually triggered by setting the TSE bit in BETA register to
“1”. The LBAT75 bit is set when the V
the pre-selected trip level, and will self clear when the V
is above the pre-selected trip level at the next detection
cycle either by manual or automatic trigger.
In Battery Mode (V
entered into battery mode by polling once every 10 minutes.
The LBAT85 detection happens automatically once when the
minute register reaches x9h or x0h minutes.
Example - When the LBAT75 is Set to “1” in Battery Mode:
The minute register changes to 30h when the device is in
battery mode, the LBAT75 is set to “1” the next time the
device switches back to Normal Mode.
Example - When the LBAT75 Remains at “0” in Battery
Mode:
If the device enters into battery mode after the minute register
reaches 49h and switches back to Normal Mode before
minute register reaches 50h, then the LBAT75 bit will remain
at “0” the next time the device switches back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12022 internally) when
the device powers up after having lost all power (defined as
V
whether V
the supplies does not set the RTCF bit to “1”. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is sufficient).
Interrupt Control Register (INT)
ADDR
DD
08h
= 0V and V
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ARST WRTC
DD
7
or V
BAT
BAT
6
BAT
DD
= 0V). The bit is set regardless of
), this bit indicates when the battery
is applied first. The loss of only one of
), this bit indicates the device has
IM
5
14
FOBATB FO3 FO2 FO1 FO0
4
BAT
has dropped below
3
2
1
BAT
0
ISL12022
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a valid
read of the respective status register (with a valid STOP
condition). When the ARST is cleared to “0”, the user must
manually reset the ALM, LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power-up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F
triggered by the alarm, as defined by the alarm registers
(0Ch to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F
set low until the ALM status bit is cleared to “0”.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the IRQ/F
battery-backup mode (i.e. V
the FOBATB is set to “1”, the IRQ/F
during battery-backup mode. This means that both the
frequency output and alarm output functions are disabled.
When the FOBATB is cleared to “0”, the IRQ/F
enabled during battery-backup mode. Note that the open
drain IRQ/F
to operate in battery-backup mode.
FREQUENCY OUT CONTROL BITS (FO<3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F
for frequency selection. Default for the ISL12022 is
FO<3:0> = 1h, or 32.768kHz output. When the frequency mode
is enabled, it will override the alarm mode at the IRQ/F
IM BIT
0
1
OUT
pin will need a pull-up to the battery voltage
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
INTERRUPT/ALARM FREQUENCY
TABLE 4.
BAT
OUT
power source active). When
OUT
OUT
pin when the RTC is
OUT
pin during
pin is disabled
pin. See Table 5
OUT
OUT
pin will be
June 23, 2009
pin is
OUT
FN6659.2
pin.