ISL62883IRTZ-T Intersil, ISL62883IRTZ-T Datasheet - Page 15

• Manufacturer Part Number: ISL62883IRTZ-T
• Description: IC REG PWM 3PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62883IRTZ-T

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 21 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 9 shows the load line implementation. The
ISL62883 drives a current source I
pin, described by Equation 1.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus sustaining the load
line accuracy with reduced cost.
I
voltage drop of:
V
line. Changing R
the load line slope. Since I
protection level, it is recommended to first scale I
based on OCP requirement, then select an appropriate
R
Differential Sensing
Figure 9 also shows the differential voltage sensing
scheme. VCCSENSE and VSSSENSE are the remote
voltage sensing signals from the processor die. A unity
gain differential amplifier senses the VSSSENSE voltage
and add it to the DAC output. The error amplifier
regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 3:
Rewriting Equation 3 and substitution of Equation 2 give:
Equation 4 is the exact equation required for load line
implementation.
The VCC
processor die. The feedback will be open circuit in the
absence of the processor. As shown in Figure 9, it is
recommended to add a “catch” resistor to feed the VR
local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output
ground to the RTN pin. These resistors, typically
10Ω~100Ω, will provide voltage feedback if the system is
powered up without a processor installed.
droop
V
I
droop
droop
droop
VCC
VCC
droop
SENSE
SENSE
flows through resistor R
is the droop voltage required to implement load
value to obtain the desired load line slope.
=
=
SENSE
2xV
----------------- -
R
R
droop
–
i
+
Cn
VSS
V
and VSS
droop
×
droop
I
SENSE
droop
=
or scaling I
V
SENSE
DAC
=
15
droop
V
DAC
+
VSS
droop
signals come from the
also sets the overcurrent
–
droop
R
SENSE
droop
droop
and creates a
can both change
×
out of the FB
I
droop
ISL62883, ISL62883B
(EQ. 4)
(EQ. 3)
(EQ. 1)
droop
(EQ. 2)
Phase Current Balancing
The ISL62883 monitors individual phase average current
by monitoring the ISEN1, ISEN2, and ISEN3 voltages.
Figure 10 shows the current balancing circuit
recommended for ISL62883. Each phase node voltage is
averaged by a low-pass filter consisting of R
presented to the corresponding ISEN pin. R
routed to inductor phase-node pad in order to eliminate
the effect of phase node parasitic PCB DCR. Equations 5
thru 7 give the ISEN pin voltages:
where R
R
inductor output side pad and the output voltage rail; and
I
The ISL62883 will adjust the phase pulse-width relative
to the other phases to make V
thus to achieve I
R
Using same components for L1, L2 and L3 will provide a
good match of R
determine R
have symmetrical layout for the power delivery path
between each inductor and the output voltage rail, such
that R
L1
pcb2
dcr1
INTERNAL
V
V
V
ISEN2
ISEN1
ISEN3
, I
TO IC
L2
FIGURE 10. CURRENT BALANCING CIRCUIT
ISEN3
ISEN2
ISEN1
= R
pcb1
and R
and I
dcr1
=
=
=
dcr2
(
(
(
= R
R
R
R
, R
pcb3
pcb1
dcr1
dcr2
dcr3
Phase3
L3
Phase1
= R
Phase2
pcb2
dcr2
are inductor average currents.
dcr1
, R
L1
Cs
Cs
Cs
+
+
+
are parasitic PCB DCR between the
dcr3
R
R
R
Rs
Rs
Rs
pcb2
= I
and R
pcb2
= R
pcb1
pcb3
, R
and R
L2
dcr2
pcb3
)
)
)
and R
×
×
×
dcr3
= I
I
I
I
L2
L1
L3
.
and R
pcb1
L3
L3
L2
L1
pcb3
are inductor DCR; R
ISEN1
, when there are
IL3
IL2
IL1
= R
dcr3
. It is recommended to
Rdcr3
Rdcr2
Rdcr1
= V
pcb2
. Board layout will
ISEN2
Rpcb3
Rpcb2
Rpcb1
= R
s
s
and C
should be
pcb3
= V
(EQ. 6)
(EQ. 5)
(EQ. 7)
V o
pcb1
.
ISEN3
FN6891.3
s
, and
,
,