ISL62882IRTZ Intersil, ISL62882IRTZ Datasheet - Page 22

• Manufacturer Part Number: ISL62882IRTZ
• Description: IC REG PWM 2PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62882IRTZ

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

board layout and current-sensing network parameters
to minimize engineering time.
V
controller to achieve good transient response. Transfer
function A
to match ω
frequencies. By forcing ω
solution, Equation 19 gives C
For example, given N = 2, R
R
L = 0.36µH, Equation 19 gives C
Assuming the compensator design is correct, Figure 18
shows the expected load transient response waveforms
if C
has a square change, the output voltage V
a square response.
If C
accurately represent real-time I
transient response. Figure 19 shows the load transient
response when C
C
FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN C
Cn
ntcs
n
=
n
n
(s) also needs to represent real-time I
is correctly selected. When the load current I
-------------------------------------------------------------- -
R
------------------------------------------
R
value is too large or too small, V
= 2.61kΩ, R
ntcnet
ntcnet
cs
L
(s) has a pole ω
×
+
and ω
WAVEFORMS
IS TOO SMALL
IS TOO LARGE
R
-------------- -
R
-------------- -
L
sum
sum
N
N
n
ntc
sns
is too small. V
×
DCR
= 10kΩ, DCR = 0.88mΩ and
so A
L
equal to ω
22
n
cs
value.
sns
o i
o i
(s) is unity gain at all
V o
V o
o i
V o
sum
and a zero ω
o
n
= 3.65kΩ, R
(s) and will worsen the
core
= 0.294µF.
sns
will sag excessively
Cn
and solving for the
(s) will not
o
ISL62882, ISL62882B
(s) for the
core
L
. One needs
p
= 11kΩ,
also has
(EQ. 19)
core
n
n
upon load insertion and may create a system failure.
Figure 20 shows the transient response when C
large. V
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
Figure 21 shows the output voltage ring back problem
during load transient response. The load current i
fast step change, but the inductor current i
accurately follow. Instead, i
system fashion due to the nature of current loop. The
ESR and ESL effect of the output capacitors makes the
output voltage V
However, the controller regulates V
droop current i
of i
causing the ring back problem. This phenomenon is not
observed when the output capacitor have very low ESR
and ESL, such as all ceramic capacitors.
Figure 22 shows two optional circuits for reduction of the
ring back.
C
constant. It usually takes the parallel of two (or more)
capacitors to get the desired value. Figure 22 shows that
two capacitors C
an optional component to reduce the V
steady state, C
FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK
n
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
L
is the capacitor used to match the inductor time
; therefore it pulls V
Rntcs
core
Rntc
is sluggish in drooping to its final value.
REDUCTION
BACK
RING
droop
n.1
Rp
n.1
o
dip quickly upon load current change.
o i
+ C
and C
, which is a real-time representation
OPTIONAL
n.2
o
L i
Cn.1
n.2
back to the level dictated by i
Rn
provides the desired C
L
are in parallel. Resistor R
responds in first order
V o
OPTIONAL
o
Rip
Cn.2
according to the
Ri
o
ring back. At
Cip
Vcn
L
ISUM+
ISUM-
cannot
n
n
is too
o
FN6890.3
has a
n
L
is
,