ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 29

• Manufacturer Part Number: ZL2105ALNF
• Description: IC DGTL DC-DC CTRLR 3A 36QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2105ALNF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 200kHz ~ 2MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9 I
The ZL2105 provides an I
that enables the user to configure all aspects of the
device operation as well as monitor the input and
output parameters. The ZL2105 can be used with any
standard 2-wire I
is compatible with SMBus version 2.0 and includes an
SALRT line to help mitigate bandwidth limitations
related to continuous fault monitoring. Pull-up resistors
are required on the I
most standard PMBus commands.
6.10 I
When communicating with multiple PMBus devices
using the I
its own unique address so the host can distinguish
between the devices. The device address can be set
according to the pin-strap options listed in Table 23.
Address values are right-justified.
Table 23. SMBus Device Address Selection
If additional device addresses are required, a resistor
can be connected to the SA pin according to Table 24
to provide up to 25 unique device addresses.
SA Pin Setting
2
C/SMBus Communications
2
C/SMBus Device Address Selection
OPEN
HIGH
LOW
2
C/SMBus interface, each device must have
2
C host device. In addition, the device
29
2
C/SMBus. The ZL2105 accepts
2
C/SMBus digital interface
SMBus Address
Reserved
0x20
0x21
ZL2105
Table 24. Additional SMBus Address Values
6.11 Phase Spreading
When multiple point of load converters share a
common DC input supply, it is desirable to adjust the
clock phase offset of each device such that not all
devices start to switch simultaneously. Setting each
converter to start its switching cycle at a different point
in time can dramatically reduce input capacitance
requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively
spread out over a period of time, the peak current
drawn at any given moment is reduced and the power
losses
dramatically.
In order to enable phase spreading, all converters must
be synchronized to the same switching clock. The CFG
pin is used to set the configuration of the SYNC pin for
each device as described in Section 5.8 “Switching
Frequency and PLL,” on Page 17.
Address
SMBus
0x2A
0x2B
0x2C
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
proportional
12.1 k
13.3 k
14.7 k
16.2 k
17.8 k
19.6 k
21.5 k
23.7 k
26.1 k
28.7 k
31.6 k
10 k
11 k
R
SA
to
the
I
Address
RMS
SMBus
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
2
March 30, 2011
are
FN6851.2
34.8 k
38.3 k
42.2 k
46.4 k
51.1 k
56.2 k
61.9 k
68.1 k
82.5 k
90.9 k
100 k
reduced
75 k
R
SA