ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 4

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection)
2, 5, 13, 14, 16, 17, 18,
1, 6, 12, 19, 24, 71
PIN NUMBER
26, 45, 55, 65
7, 8, 11, 72
27, 36, 56
30, 31
20, 21
28, 29
32, 33
34, 35
37, 38
39, 40
41, 42
43, 44
47, 48
49, 50
51, 52
53, 54
57, 58
59, 60
61, 62
63, 64
9, 10
3, 4
PD
15
22
23
25
46
66
67
68
69
70
D10N, D10P [NC, D10] LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10]
D11N, D11P [NC, D11] LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11]
CLKOUTN, CLKOUTP
4
ORN, ORP [NC, OR]
D0N, D0P [NC, D0]
D1N, D1P [NC, D1]
D2N, D2P [NC, D2]
D3N, D3P [NC, D3]
D4N, D4P [NC, D4]
D5N, D5P [NC, D5]
D6N, D6P [NC, D6]
D7N, D7P [NC, D7]
D8N, D8P [NC, D8]
D9N, D9P [NC, D9]
LVDS [LVCMOS]
[NC, CLKOUT]
CLKDIVRSTP,
CLKDIVRSTN
CLKP, CLKN
VINN, VINP
OUTMODE
OUTFMT
RESETN
NAPSLP
RLVDS
NAME
OVDD
AVDD
OVSS
AVSS
AVSS
SCLK
SDIO
DNC
VCM
SDO
RES
CSB
1.8V Analog Supply
Do Not Connect
Reserved. (4.7kΩ pull-up to OVDD is required for each of these pins)
Common Mode Output
Tri-Level Output Mode (LVDS, LVCMOS)
Tri-Level Power Control (Nap, Sleep modes)
Power On Reset (Active Low)
1.8V Output Supply
Sample Clock Synchronous Divider Reset Positive, Negative
LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1]
LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2]
LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3]
LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4]
LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5]
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT]
LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6]
LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7]
LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8]
LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9]
LVDS Over Range Complement, True [NC, LVCMOS Over Range]
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Tri-Level Output Data Format (Two’s Comp., Gray Code, Offset Binary)
Exposed Paddle. Analog Ground
Analog Ground
Analog Input Negative, Positive
Clock Input True, Complement
Output Ground
LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0]
ISLA112P50
LVDS [LVCMOS] FUNCTION
June 17, 2010
FN7604.1