ISL8200MEVAL2PHZ Intersil, ISL8200MEVAL2PHZ Datasheet - Page 18

• Manufacturer Part Number: ISL8200MEVAL2PHZ
• Description: EVAL BOARD FOR ISL8200M
• Manufacturer: Intersil

Specifications of ISL8200MEVAL2PHZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

By connecting the FSYNC_IN pin to an external square
pulse waveform (such as the CLKOUT signal, typically
50% duty cycle from another ISL8200M), the
ISL8200M will synchronize its switching frequency to
the fundamental frequency of the input waveform. The
maximum voltage to the FSYNC_IN pin is V
The Frequency Synchronization feature will
synchronize the leading edge of the CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal.
CLKOUT is not available until the PLL locks.
The locking time is typically 130µs for F
EN is not released for a soft-start cycle until FSYNC is
stabilized and the PLL is in locking. It is recommended
to connect all EN pins together in multiphase
configuration.
The loss of a synchronization signal for 13 clock cycles
causes the IC to be disabled until the PLL returns
locking, at which point a soft-start cycle is initiated and
normal operation resumes. Holding FSYNC_IN low will
disable the IC.
Setting Relative Phase-Shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by
the VCC resistor divider output, the ISL8200M operates
with CLKOUT phase shifted, as shown in Table 3. The
phase shift is latched as V
cannot be changed on the fly.
PH_CNTRL RANGE
29% to 45% of V
45% to 62% of V
<29% of V
1500
1400
1300
1200
1100
1000
FIGURE 27. RFS-ext vs SWITCHING FREQUENCY
DECODING
62% to V
900
800
700
0
CC
CC
CC
CC
100
PHASE for CLKOUT
WRT CHANNEL 1
TABLE 3.
RFS-ext (kΩ)
18
CC
200
120°
180°
-60°
raises above POR so it
90°
300
SW
REQUIRED
PH_CNTRL
= 500kHz.
CC
15% V
37% V
53% V
400
V
+ 0.3V.
CC
ISL8200M
CC
CC
CC
Layout Guide
To achieve stable operation, low losses, and good
thermal performance some layout considerations are
necessary.
• The ground connection between PGND1 (pin 15) and
• Place a high frequency ceramic capacitor between
• Use large copper areas for power path (PVIN, PGND,
• Keep the trace connection to the feedback resistor
• Use remote sensed traces to the regulation point to
• Avoid routing any sensitive signal traces, such as the
• FSYNC_IN is a sensitive pin. If it not use for
PGND (pin 18) should be a solid ground plane under
the module.
(1) PVIN and PGND (pin 18) and (2) a 10µF between
PVCC and PGND1 (pin 15) as close to the module as
possible to minimize high frequency noise. High
frequency ceramic capacitors close to the module
between VOUT and PGND will help to minimize noise
at the output ripple.
VOUT) to minimize conduction loss and thermal
stress. Also, use multiple vias to connect the power
planes in different layers.
short.
achieve a tight output voltage regulation, and keep
them in parallel. Route a trace from VSEN_REM- to a
location near the load ground, and a trace from
feedback resistor to the point-of-load where the tight
output voltage is desire.
VOUT and VSENREM- sensing point near the PHASE
pin.
receiving external synchronization signal, then keep
the trace connecting to the pin short. A bypass
capacitor value 100pF connecting between
FSYNC_IN pin and GND1 can help to bypass the
noise sensitivity on the pin.
CPVCC
CEN
PV
FIGURE 28. RECOMMENDED LAYOUT
IN
CIN
PGND
COUT
RFBT
V
Load GND
OUT
February 26, 2010
VOUT
To
To
FN6727.1