DP83865DVH National Semiconductor, DP83865DVH Datasheet - Page 5

• Manufacturer Part Number: DP83865DVH
• Description: 10/100/1000BASE-T TRANSCEIVER, SMD
• Manufacturer: National Semiconductor

Specifications of DP83865DVH

• Data Rate: 1000Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u, IEEE 802.3z
• Supply Current: 430µA
• Supply Voltage Range: 2.375V To 2.625V, 3.135V To 3.465V
• Operating Temperature Range: 0°C To +70°C
• Interface Type: GMII, MII, RGMII
• Rohs Compliant: Yes
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.0 Pin Description
The DP83865 pins are classified into the following interface
categories (each is described in the sections that follow):
— MAC Interfaces
— Management Interface
— Media Dependent Interface
— JTAG Interface
— Clock Interface
— Device Configuration and LED Interface
— Reset
— Power and Ground Pins
— Special Connect Pins
1.1 MAC Interfaces (MII, GMII, and RGMII)
CRS/RGMII_SEL0
COL/CLK_MAC_FREQ O_Z,
TX_CLK/RGMII_SEL1
Signal Name
S, PD
S, PD
S, PD
Type
O_Z,
O_Z,
PQFP
Pin #
40
39
60
CARRIER SENSE or RGMII SELECT: CRS is asserted high to indicate the
presence of a carrier due to receive or transmit activity in Half Duplex mode.
For 10BASE-T and 100BASE-TX Full Duplex operation CRS is asserted when
a received packet is detected. This signal is not defined for 1000BASE-T Full
Duplex mode.
In RGMII mode, the CRS is not used. This pin can be used as a RGMII strap-
ping selection pin.
COLLISION DETECT: Asserted high to indicate detection of a collision condi-
tion (assertion of CRS due to simultaneous transmit and receive activity) in
Half Duplex modes. This signal is not synchronous to either MII clock
(GTX_CLK, TX_CLK or RX_CLK). This signal is not defined and stays low for
Full Duplex modes.
CLOCK TO MAC FREQUENCY Select:
1 = CLOCK TO MAC output is 125 MHz
0 = CLOCK TO MAC output is 25 MHz
TRANSMIT CLOCK or RGMII SELECT: TX_CLK is a continuous clock signal
generated from reference CLK_IN and driven by the PHY during 10 Mbps or
100 Mbps MII mode. TX_CLK clocks the data or error out of the MAC layer and
into the PHY.
The TX_CLK clock frequency is 2.5 MHz in 10BASE-T and 25 MHz in
100BASE-TX mode.
Note: “TX_CLK” should not be confused with the “TX_TCLK” signal.
In RGMII mode, the TX_CLK is not used. This pin can be used as a RGMII
strapping selection pin. This pin should be pulled high for RGMII interface.
RGMII_SEL1 RGMII_SEL0
0
0
1
1
5
0
1
0
1
Type: I
Type: O
Type: O_Z
Type: I/O_Z
Type: S
Type: PU
Type: PD
Description
MAC Interface
= GMII
= GMII
= RGMII - HP
= RGMII - 3COM
Inputs
Output
Tristate Output
Tristate Input_Output
Strapping Pin
Internal Pull-up
Internal Pull-down
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