ISL34321INZ Intersil, ISL34321INZ Datasheet - Page 3

• Manufacturer Part Number: ISL34321INZ
• Description: Transceiver IC
• Manufacturer: Intersil

Specifications of ISL34321INZ

• Serdes Function: Transmitter / Receiver
• No. Of Inputs: 16
• No. Of Outputs: 16
• Supply Voltage Range: 1.7V To 1.9V, 3V To 3.6V
• Driver Case Style: TQFP
• No. Of Pins: 48
• Frequency: 45MHz
• Interface: I2C
• Termination Type: SMD
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
PIN NUMBER
47, 46
45, 44
43, 42
41, 40
33, 32
24, 23
25, 26
37, 48
9, 8
7, 6
5, 4
3, 2
16
17
15
20
39
18
19
27
12
10
28
21
35
31
29
13
14
34
30
I2CA[1:0] (Note 1) I
GND_CDR (Note 2) Analog (Serial) Data Recovery Ground
SDA, SCL (Note 1)
GND_AN (Note 2)
GND_CR (Note 2)
GND_TX (Note 2)
GND_IO (Note 2)
SERIOP, SERION
GND_P (Note 2)
RGBA7, RGBA6
RGBA5, RGBA4
RGBA3, RGBA2
RGBA1, RGBA0
RGBC7, RGBC6
RGBC5, RGBC4
RGBC3, RGBC2
RGBC1, RGBC0
VHSYNCPOL
PIN NAME
PCLK_OUT
VIDEO_TX
RSTB/PDB
REF_RES
PCLK_IN
VDD_CR
VDD_TX
VDD_AN
DATAEN
MASTER
STATUS
HSYNC
VSYNC
3
Parallel video data LVCMOS inputs with
Hysteresis
Horizontal (line) Sync LVCMOS input with
Hysteresis
Vertical (frame) Sync LVCMOS input with
Hysteresis
Video Data Enable LVCMOS input with
Hysteresis
Pixel clock LVCMOS input
Default; not used
High-speed differential serial I/O
CMOS input for HSYNC and VSYNC Polarity
1: HSYNC & VSYNC active low
0: HSYNC & VSYNC active high
CMOS input for video flow direction
1: video serializer
0: video deserializer
I
I
1: Master
0: Slave
CMOS input for Reset and Power-down. For normal operation, this pin must be forced
high. When this pin is forced low, the device will be reset. If this pin stays low, the device
will be in PD mode.
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: otherwise
Note: serializer and deserializer switch roles during side-channel reverse traffic
Analog bias setting resistor connection; use 3.16kΩ ±1% to ground
PLL Ground
Digital (Parallel and Control) Ground
Analog (Serial) Output Ground
Analog Bias Ground
Core Logic Ground
Core Logic VDD
Analog (Serial) Output VDD
Analog Bias VDD
2
2
2
C Interface Pins (I
C Device Address
C Master Mode
SERIALIZER
ISL34321
2
C DATA, I
2
C CLK)
DESCRIPTION
Parallel video data LVCMOS outputs
Horizontal (line) Sync LVCMOS output
Vertical (frame) Sync LVCMOS output
Video Data Enable LVCMOS output
PLL reference clock LVCMOS input
Recovered clock LVCMOS output
High speed differential serial I/O
DESERIALIZER
September 23, 2010
FN6870.1