SC16C652BIB48 NXP Semiconductors, SC16C652BIB48 Datasheet - Page 15

• Manufacturer Part Number: SC16C652BIB48
• Description: IC, UART, DUAL, 32BYTE FIFO, 16C652
• Manufacturer: NXP Semiconductors

Specifications of SC16C652BIB48

• No. Of Channels: 2
• Data Rate: 5Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 48
• Svhc: No SVHC (18-Jun-2010)
• Uart Features: Independent Transmit & Receive UART Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
7. Register descriptions
Table 9:
[1]
[2]
[3]
[4]
[5]
SC16C652B_4
Product data sheet
A2 A1 A0 Register Default
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
Enhanced Register Set
0
1
1
1
1
The value shown in represents the register’s initialized HEX value; X = not applicable.
This bit is only accessible when EFR[4] is set.
Accessible only when LCR[7] is logic 0.
Baud rate registers accessible only when LCR[7] is logic 1.
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
SC16C652B internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
EFR
Xon-1
Xon-2
Xoff-1
Xoff-2
[4]
[3]
Table 9
assigned bit functions are more fully defined in
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
00
00
00
00
00
[5]
[1]
details the assigned bit functions for the SC16C652B internal registers. The
Bit 7
bit 7
bit 7
CTS
interrupt
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
clock
select
FIFO
data
error
CD
bit 7
bit 7
bit 15
Auto
CTS
bit 7
bit 15
bit 7
bit 15
[2]
[2]
Bit 6
bit 6
bit 6
RTS
interrupt
RCVR
trigger
(LSB)
FIFOs
enabled
set break set parity even
IRDA
enable
THR and
TSR
empty
RI
bit 6
bit 6
bit 14
Auto RTS special
bit 6
bit 14
bit 6
bit 14
[2]
Rev. 04 — 1 September 2005
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Bit 5
bit 5
bit 5
Xoff
interrupt
TX
trigger
(MSB)
INT
priority
bit 4
0
THR
empty
DSR
bit 5
bit 5
bit 13
character
select
bit 5
bit 13
bit 5
bit 13
[2]
[2]
Bit 4
bit 4
bit 4
Sleep
mode
TX trigger
(LSB)
INT
priority
bit 3
parity
loop back OP2/INT
break
interrupt
CTS
bit 4
bit 4
bit 12
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
bit 4
bit 12
bit 4
bit 12
[2]
[2]
Section 7.1
Bit 3
bit 3
bit 3
modem
status
interrupt
Rx
DMA
mode
select
INT
priority
bit 2
parity
enable
enable
framing
error
bit 3
bit 3
bit 11
Cont-3
Tx, Rx
Control
bit 3
bit 11
bit 3
bit 11
CD
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
through
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
(OP1)
parity
error
bit 2
bit 2
bit 10
Cont-2
Tx, Rx
Control
bit 2
bit 10
bit 2
bit 10
RI
SC16C652B
Section
Bit 1
bit 1
bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
Cont-1
Tx, Rx
Control
bit 1
bit 9
bit 1
bit 9
DSR
7.11.
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
Control
bit 0
bit 8
bit 0
bit 8
CTS
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