STA339BWS13TR STMicroelectronics, STA339BWS13TR Datasheet
STA339BWS13TR
Specifications of STA339BWS13TR
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STA339BWS13TR Summary of contents
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... Preset night-time listening mode Individual channel soft/hard mute Table 1. Device summary Order code STA339BWS STA339BWS13TR March 2010 Independent channel volume and DSP bypass input data interface Input and output channel mapping Automatic invalid input-detect mute ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA339BWS 6.1 Configuration registers (addr 0x00 to 0x05 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Volume ...
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Contents 6.7.8 6.7.9 6.8 Variable max power correction registers (addr 0x27 - 0x28 6.9 Distortion compensation registers (addr 0x29 - 0x2A ...
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STA339BWS List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA339BWS Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STA339BWS is an integrated solution of digital audio processing, digital amplifier controls and power output stage to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The ...
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STA339BWS regardless of output power level. This feature separates the audio frequency band into two sub-bands independently processed to provide better sound clarity and to avoid speaker saturation. The serial audio data input interface accepts all possible formats, including the ...
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Pin connections 2 Pin connections 2.1 Connection diagram Figure 2. Pin connection PowerSSO-36 (top view) GND_SUB TEST_MODE VCC_REG GND_REG OUT3B / FFX3B OUT3A / FFX3A 2.2 Pin description Table 2. Pin description Pin Type 1 GND ...
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STA339BWS Table 2. Pin description (continued) Pin Type 11 Power 12 GND GND 15 Power I/O 21 Power 22 GND Power GND ...
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Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V Power supply voltage (pins VCCx Digital supply voltage (pins VDD_DIG PLL supply voltage (pin VDD_PLL Operating junction temperature ...
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STA339BWS 3.3 Recommended operating conditions Table 5. Recommended operating condition Symbol V Power supply voltage (VCCxA, VCCxB Digital supply voltage DD_DIG V PLL supply voltage DD_PLL T Ambient temperature amb 3.4 Electrical specifications for the digital section Table ...
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Electrical specifications 3.5 Electrical specifications for the power section The specifications given in this section are valid for the operating conditions kHz 384 kHz Table 7. Electrical specifications - power section Symbol ...
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STA339BWS Figure 3. Test circuit Duty cycle = 50% INxY OUTxY tr +Vcc M58 Ω OUTxY R 8 M57 gnd Doc ID 15276 Rev 3 Electrical specifications VCC (0.9)*VCC ½VCC (0.1)*VCC V67 - vdc = Vcc/2 15/76 ...
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Electrical specifications 3.6 Power on/off sequence Figure 4. Power-on sequence VCC VCC VCC VCC VCC VDD_Dig VDD_Dig VDD_Dig VDD_Dig VDD_Dig XTI XTI XTI XTI XTI Reset Reset Reset Reset Reset ...
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STA339BWS 4 Processing data paths Figure 6 and Figure 7 whole processing chain is composed of two consecutive sections. In the first one, dual-channel processing is implemented and in the second section each channel is fed into the post-mixing block ...
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Processing data paths Figure 7. Left and right processing, section 2 Dual-band DRC enabled Dual-band DRC disabled 18/76 Volume Volume C1Mx1 = C1Mx1 = ...
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STA339BWS bus specification The STA339BWS supports the I slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that ...
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I C bus specification 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA339BWS acknowledges this and then waits for the byte of internal address. After ...
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STA339BWS 5.4.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA339BWS. The master acknowledges each data byte read and then generates a STOP condition ...
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Register description 6 Register description Note: Addresses exceeding the maximum address number must not be written. Table 8. Register summary Addr Name D7 0x00 CONFA FDRB 0x01 CONFB C2IM 0x02 CONFC OCRB 0x03 CONFD SME 0x04 CONFE SVE 0x05 CONFF ...
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STA339BWS Table 8. Register summary (continued) Addr Name D7 0x1F A1CF3 0x20 A2CF1 0x21 A2CF2 0x22 A2CF3 0x23 B0CF1 0x24 B0CF2 0x25 B0CF3 0x26 CFUD 0x27 MPCC1 0x28 MPCC2 0x29 DCC1 0x2A DCC2 0x2B FDRC1 0x2C FDRC2 0x2D STATUS PLLUL ...
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Register description 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00 FDRB TWAB 0 1 Master clock select Table 9. Master clock select Bit R/W 0 R/W 1 R/W 2 R/W The STA339BWS supports ...
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STA339BWS The STA339BWS has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation ...
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Register description Fault detect recovery bypass Table 15. Fault detect recovery bypass Bit R/W 7 R/W 0 The on-chip power block provides feedback to the digital controller which is used to indicate a fault condition (either overcurrent or thermal). When ...
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STA339BWS Table 18. Support serial audio input formats for MSB-first (SAIFB = 0) BICKI Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) BICKI ...
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Register description Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) (continued) BICKI make the STA339BWS work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It ...
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STA339BWS Channel input mapping Table 21. Channel input mapping Bit R R/W 1 Each channel received via I Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers maps each ...
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Register description Table 24. Compensating pulse size CSZ[3:0] 0000 0001 … 1111 Overcurrent warning adjustment bypass Table 25. Overcurrent warning bypass Bit R/W 7 R/W 1 The OCRB is used to indicate how STA339BWS behaves when an overcurrent warning condition ...
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STA339BWS De-emphasis Table 27. De-emphasis Bit R/W 1 R/W 0 DSP bypass Table 28. DSP bypass Bit R/W 2 R/W 0 Setting the DSPB bit bypasses the EQ function of the STA339BWS. Postscale link Table 29. Postscale link Bit R/W ...
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Register description Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the ...
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STA339BWS Setting the MPC bit turns on special processing that corrects the STA339BWS power device at high power. This mode should lower the THD full FFX system at maximum power output and slightly below. If enabled, MPC is ...
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Register description Zero-crossing volume enable Table 40. Zero-crossing volume enable Bit R/W RST 6 R/W 1 The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible. Soft volume update enable Table 41. ...
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STA339BWS Table 43. Output configuration engine selection OCFG[1: Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any ...
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Register description Figure 11. OCFG = 01 Figure 12. OCFG = 10 Figure 13. OCFG = 11 The STA339BWS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot ...
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STA339BWS Figure 14. Output mapping scheme FFX ™ FFX ™ FFX ™ FFX ™ FFX ™ FFX ™ modulator modulator modulator modulator modulator modulator For each configuration the PWM signals from the digital driver are mapped in different ways to ...
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Register description 2.0 channels, two full-bridges (OCFG = 00) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B Default modulation: FFX1A/1B configured as ternary ...
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STA339BWS 2.1 channels, two half-bridges + one full-bridge (OCFG = 01) Mapping: FFX1A -> OUT1A FFX2A -> OUT1B FFX3A -> OUT2A FFX3B -> OUT2B FFX1A -> OUT3A FFX1B -> OUT3B FFX2A -> OUT4A FFX2B -> OUT4B Modulation: FFX1A/1B configured as ...
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Register description 2.1 channels, two full-bridges + one external full-bridge (OCFG = 10) Mapping: FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B EAPD -> OUT4A TWARN -> OUT4B Default modulation: ...
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STA339BWS Invalid input detect mute enable Table 44. Invalid input detect mute enable Bit R/W 2 R/W 1 Setting the IDE bit enables this function, which looks at the input I mutes if the signals are perceived as invalid. Binary ...
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Register description The PWDN register is used to place the low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power-stage, ...
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STA339BWS 6.2.1 Mute/line output configuration register (addr 0x06 LOC1 LOC0 0 0 Table 50. Line output configuration LOC[1: Line output is only active when OCFG = 00. In this case LOC determines the line output ...
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Register description 6.2.5 Channel 3 / line output volume (addr 0x0A C3VOL7 C3VOL6 0 1 Table 52. Channel volume as a function of CxVOL[7:0] CxVOL[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) … 01011111 (0x5F) 01100000 (0x60) 01100001 (0x61) ...
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STA339BWS 6.3 Audio preset registers (addr 0x0B and 0x0C) 6.3.1 Audio preset register 1 (addr 0x0B Reserved Reserved 1 0 Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. ...
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Register description Table 55. Audio preset AM switching frequency selection (continued) AMAM[2:0] 101 110 Bass management crossover Table 56. Bass management crossover Bit R R/W 0 Table 57. Bass management ...
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STA339BWS 6.4 Channel configuration registers (addr 0x0E - 0x10 C1OM1 C1OM0 C2OM1 C2OM0 C3OM1 C3OM0 1 0 Tone control bypass Tone control (bass/treble) can be bypassed on a per channel ...
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Register description Binary output enable registers Each individual channel output can be set to output a binary PWM stream. In this mode output channel is considered the positive output and output B is negative inverse. Table 61. ...
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STA339BWS 6.5 Tone control register (addr 0x11 TTC3 TTC2 0 1 Tone control Table 64. Tone control boost/cut as a function of BTC and TTC bits BTC[3:0]/TTC[3:0] 0000 0001 0010 … 0101 0110 0111 1000 1001 … 1100 ...
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Register description 6.6.3 Limiter 2 attack/release rate (addr 0x14 L2A3 L2A2 0 1 6.6.4 Limiter 2 attack/release threshold (addr 0x15 L2AT3 L2AT2 0 1 6.6.5 Description The STA339BWS includes two independent limiter blocks. The purpose of ...
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STA339BWS release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the ...
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Register description Table 66. Limiter release rate vs LxR bits LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Anti-clipping mode Table 67. Limiter attack threshold vs LxAT bits (AC mode) LxAT[3:0] ...
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STA339BWS Table 67. Limiter attack threshold vs LxAT bits (AC mode) (continued) LxAT[3:0] 1110 1111 Table 68. Limiter release threshold vs LxRT bits (AC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 ...
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Register description Table 69. Limiter attack threshold vs LxAT bits (DRC mode) (continued) LxAT[3:0] 1001 1010 1011 1100 1101 1110 1111 Table 70. Limiter release threshold vs LxRT bits (DRC mode) LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 ...
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STA339BWS 6.6.7 Limiter 1 extended release threshold (addr 0x33 ERTHEN1 ERTH1[ The extended release threshold value is determined as follows: release threshold = -12 + ERTH1 / 4 6.6.8 Limiter 2 extended attack threshold (addr 0x34) ...
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Register description D7 D6 C1B7 C1B6 0 0 6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C C2B23 C2B22 C2B15 C2B14 C2B7 C2B6 0 0 6.7.4 Coefficient a1 data ...
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STA339BWS 6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25 C5B23 C5B22 C5B15 C5B14 C5B7 C5B6 0 0 6.7.7 Coefficient read/write control register (addr 0x26 6.7.8 Description ...
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Register description Reading a coefficient from RAM 1. Select the RAM block with register 0x31 bit1, bit0. 2. Write 6-bits of address Write bit Read top 8-bits of coefficient in I ...
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STA339BWS Writing a set of coefficients to RAM 1. Select the RAM block with register 0x31 bit1, bit0. 2. Write 6-bits of starting address Write top 8-bits of coefficient Write middle 8-bits of ...
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Register description Table 71. RAM block for biquads, mixing, scaling, bass management (continued) Index Index (Hex) (Decimal) 40 0x28 41 0x29 42 0x2A 43 0x2B 44 0x2C 45 0x2D 46 0x2E 47 0x2F 48 0x30 49 0x31 50 0x32 51 ...
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STA339BWS Coefficients stored in the user defined coefficient RAM are referenced in the following manner: CxHy0 = b 1 CxHy1 = b 2 CxHy2 = -a 1 CxHy3 = -a 2 CxHy4 = b 0 where x represents the channel ...
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Register description 6.8 Variable max power correction registers (addr 0x27 - 0x28 MPCC15 MPCC14 MPCC7 MPCC6 1 1 MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in ...
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STA339BWS 6.11 Device status register (addr 0x2D PLLUL FAULT This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault ...
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Register description 6.12 EQ coefficients and DRC configuration register (addr 0x31 XOB Reserved RAM Table 73. EQ RAM select SEL[1: DRC / Anti clipping Bits AMGC[3:2] change the behavior of ...
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STA339BWS 6.13 Extended configuration register (addr 0x36 MDRC[1] MDRC[ Extended configuration register provides access to B 6.13.1 Dual-band DRC (B STA339BWS device provide a dual-band DRC (B path, as depicted in 2 Figure 19. B DRC ...
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Register description For the user programmable mode, use the formulae below to compute the high pass filters alpha -(1 + alpha where alpha = (1-sin(ω A first-order ...
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STA339BWS Figure 20. EQDRC scheme Channel In Channel In Channel In Channel In Channel In Channel In Channel In Channel In Extended postscale range Table 76. Bit PS48DB description PS48DB 0 1 Postscale is an attenuation by default. When PS48DB ...
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Register description Table 79. Bit BQ5 description BQ5 0 1 Table 80. Bit BQ6 description BQ6 0 1 Table 81. Bit BQ7 description BQ7 0 1 When filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are ...
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STA339BWS When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the following formula: Fade-in rate = dB/ms where N is the SVUP[4:0] value. Table 83. Bit SVDWE description SVDWE ...
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Applications 7 Applications 7.1 Applications schematic Figure 21 below shows the typical applications schematic for STA339BWS. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible ...
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... STA339BWS 7.3 Typical output configuration Figure 22 shows the typical output configuration used for BTL stereo mode. Please contact STMicroelectronics for other recommended output configurations. Figure 22. Output configuration for stereo BTL mode (R OUT1A OUT1A OUT1A OUT1B OUT1B OUT1B OUT2A OUT2A OUT2A OUT2B ...
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Package thermal characteristics 8 Package thermal characteristics Using a double-layer PCB the thermal resistance, junction to ambient, with 2 copper ground areas The dissipated power within the device depends primarily on the supply voltage, load ...
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STA339BWS 9 Package mechanical data Figure 24 shows the package outline and Figure 24. PowerSSO-36 EPD outline drawing Table 84 gives the dimensions. Doc ID 15276 Rev 3 Package mechanical data 73/76 ...
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Package mechanical data Table 84. PowerSSO-36 EPD dimensions Symbol Min A 2.15 A2 2.15 a1 0.00 b 0.18 c 0.23 D 10. 10. 0.60 ...
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STA339BWS 10 Revision history Table 85. Document revision history Date 10-Dec-2008 16-Feb-2009 01-Mar-2010 Revision 1 Initial release. Updated names/descriptions for pins 17-20 in Added cross reference to I on/off sequence on page 18 2 Added Figure 4: Power-off sequence for ...
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