STA339BWS13TR STMicroelectronics, STA339BWS13TR Datasheet - Page 57

• Manufacturer Part Number: STA339BWS13TR
• Description: DIG AUDIO SYSTEM, 2-CH, 36POWERSSOP
• Manufacturer: STMicroelectronics

Specifications of STA339BWS13TR

• Svhc: No SVHC (15-Dec-2010)
• No. Of Pins: 36
• Operating Temperature Range: -20°C To +70°C
• Supply Voltage Max: 21.5V
• Supply Voltage Min: 4.5V
• Termination: RoHS Compliant
• Package / Case: PowerSSO
• Interface: I2C
• Interface Type: I2C
• Rohs Compliant: Yes

STA339BWS
6.7.6
6.7.7
6.7.8
Note:
Coefficient b0 data register bits (addr 0x23 - 0x25)
Coefficient read/write control register (addr 0x26)
Description
Coefficients for user-defined EQ, mixing, scaling, and bass management are handled
internally in the STA339BWS via RAM. Access to this RAM is available to the user via an
I
contains a coefficient base address, five sets of three store the values of the 24-bit
coefficients to be written or that were read, and one contains bits used to control the
write/read of the coefficient(s) to/from RAM.
Three different RAM banks are embedded in STA339BWS. The three banks are managed in
paging mode using EQCFG register bits. They can be used to store different EQ settings.
For speaker frequency compensation, a sampling frequency independent EQ must be
implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and
downloading them into the three RAM banks, it is possible to select the suitable RAM block
depending from the incoming frequency with a simple I
For example, in case of different input sources (different sampling rates), the three different
sets of coefficients can be downloaded once at the start up, and during the normal play it is
possible to switch among the three RAM blocks allowing a faster operation, without any
additional download from the microcontroller.
To write the coefficients in a particular RAM bank, this bank must be selected first writing
bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.
Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to
the coefficients stored in the active RAM block.
The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.
2
C register interface. A collection of I
C5B23
C5B15
C5B7
D7
D7
D7
D7
0
0
0
C5B22
C5B14
C5B6
D6
D6
D6
D6
0
0
0
Reserved
0
C5B21
C5B13
C5B5
D5
D5
D5
D5
0
0
0
Doc ID 15276 Rev 3
2
C5B20
C5B12
C5B4
C registers are dedicated to this function. One
D4
D4
D4
D4
0
0
0
C5B19
C5B11
C5B3
D3
D3
D3
D3
RA
0
0
0
0
2
C write operation on register 0x31.
C5B18
C5B10
C5B2
D2
D2
D2
D2
R1
0
0
0
0
Register description
C5B17
C5B9
C5B1
WA
D1
D1
D1
D1
0
0
0
0
C5B16
C5B8
C5B0
W1
D0
D0
D0
D0
0
0
0
0
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