M52S128168A-7.5BG ELITE SEMICONDUCTOR, M52S128168A-7.5BG Datasheet

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... ESMT Revision History Revision 1.0 (May. 29, 2007) -Original Revision 1.1 (Oct. 08, 2007) -Add Speed -7 spec. -Modify Icc spec Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 1/47 ...

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... BA0 20 BA1 / Elite Semiconductor Memory Technology Inc. ORDERING INFORMATION PRODUCT NO. M52S128168A-7TG M52S128168A-7BG M52S128168A-7.5TG 133MHz M52S128168A-7.5BG 133MHz M52S128168A-10TG M52S128168A-10BG VSSQ A VSS DQ15 DQ15 V SSQ B DQ14 DQ14 DQ13 DQ13 V DDQ C DQ12 DQ11 DQ12 DQ11 D DQ10 DQ9 V SSQ DQ10 E DQ8 NC DQ9 V DDQ DQ8 ...

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... Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M52S128168A Bank D Bank C Bank B Bank A ...

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... ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 25 C ° 1MHZ) SYMBOL C IN1 C IN2 C OUT M52S128168A VALUE -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 ° MAX UNIT 2 +0.3 V DDQ 0 0.2 V μ μ MIN MAX 1 ...

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... CLK V (max Input signals are stable I = 0mA, Page Burst OL All Band Activated, tCCD = tCCD (min) ≥ (min -N/L -G/F TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52S128168A CAS Version Latency -7 -7.5 80 0.5 ∞ = 0.5 =10ns 10 ∞ ∞ =15ns 25 ∞ ...

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... RCD t (min (min) RAS t (max) RAS t (min (min) RFC t (min) CDL t (min) RDL t (min) BDL t (min) CCD t (min) MRD CAS latency=3 CAS latency=2 t (max) REF after self refresh exit. rfc M52S128168A Unit / 0 DDQ ns V DDQ Version Unit -7 -7.5 - 100 ...

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... Elite Semiconductor Memory Technology Inc. -7 Symbol Min Max Min 7 1000 7 5.5 t SAC 7 t 2.5 2 2.5 2 2.5 2 SLZ 5.5 t SHZ 7 *All AC parameters are measured from half to half. M52S128168A -7.5 -10 Unit Max Min Max 10 1000 1000 2 2 Publication Date: Oct. 2007 Revision: 1.1 Note 7/47 ...

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... Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2) Elite Semiconductor Memory Technology Inc. CKEn-1 CKEn CS RAS CAS Entry Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M52S128168A DQM BA0 WE A10/AP A9~A0 BA1 CODE Row Address L Column Address H (A0~A8) L Column Address H (A0~A8 ...

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... Elite Semiconductor Memory Technology Inc CAS Latency CAS Latency Burst Type Latency Reserved Reserved Reserved Reserved Reserved Reserved M52S128168A Burst Length Burst Length Type Sequential Interleave Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Full Page Length : 512 Publication Date: Oct. 2007 Revision: 1 ...

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... If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored has +/-5°C tolerance Elite Semiconductor Memory Technology Inc PASR DS M52S128168A Address bus Extended Mode Register Set A2-A0 Self Refresh Coverage 000 4Bank 001 2 Bank (BankA& BankB) or (BA1=0) PASR 010 1 Bank (BankA) or ...

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... ESMT BURST SEQUENCE (BURST LENGTH = 4) Initial Adrress BURST SEQUENCE (BURST LENGTH = 8) Initial Elite Semiconductor Memory Technology Inc. Sequential Sequential M52S128168A Interleave Interleave Publication Date: Oct. 2007 Revision: 1 11/47 ...

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... CS high. CS high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored. Elite Semiconductor Memory Technology Inc. M52S128168A MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the ...

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... Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. M52S128168A after the last data input to RDL is defined as the minimum number of clock RP ...

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... The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of t RAS reaches idle state to begin normal operation. with clock cycle RFC M52S128168A before the SDRAM RFC Publication Date: Oct. 2007 Revision: 1.1 14/47 ...

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... The DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM’s RAS falling. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 15/47 ...

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... Read command ( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 16/47 ...

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... Before executing self refresh, all banks must be precharged. Burst stop command ( Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 17/47 ...

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... ESMT No operation ( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 18/47 ...

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... BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend DQM Operation *Note :1. CKE to CLK disable/enable = 1CLK. 2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”. 3. DQM masks both data-in and data-out. Elite Semiconductor Memory Technology Inc M52S128168A Publication Date: Oct. 2007 Revision: 1 19/47 ...

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... By “interrupt” is meant to stop burst read/write by external before the end of burst. By ” CAS interrupt ”, to stop burst read/write by CAS access; read and write CAS to CAS delay. (=1CLK) CCD Last data in to new column address delay. (=1CLK) CDL Elite Semiconductor Memory Technology Inc M52S128168A Publication Date: Oct. 2007 Revision: 1.1 20/47 ...

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... ESMT 4. CAS Interrupt (II) : Read Interrupted by Write & DQM ( Elite Semiconductor Memory Technology Inc M52S128168A D 3 Publication Date: Oct. 2007 Revision: 1.1 21/47 ...

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... To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of four banks operation. Elite Semiconductor Memory Technology Inc M52S128168A Publication Date: Oct. 2007 Revision: 1.1 22/47 ...

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... The row active command of the precharge bank can be issued after t The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc M52S128168A from this point. RP Publication Date: Oct ...

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... Precharge can be issued here or earlier (satisfying t 6. PRE : All banks precharge, if necessary. MRS can be issued only at all banks precharge state. Elite Semiconductor Memory Technology Inc determinates the last data write. RDL min delay) with DQM. RAS M52S128168A * Publication Date: Oct. 2007 Revision: 1.1 24/47 ...

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... During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state. For the time interval of t RFC Elite Semiconductor Memory Technology Inc from self refresh exit command, any other command can not be accepted. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 25/47 ...

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... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 26/47 ...

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... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M52S128168A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Row Active) Row Active) Row Active) Row Active) Publication Date: Oct. 2007 Revision: 1.1 Note 2 2 ...

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... X ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M52S128168A ACTION Idle after tRP Idle after tRP Idle after tRP Row Active after tRCD Row Active after tRCD Idle after tRFC Idle after tRFC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Oct. 2007 Revision: 1 ...

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... Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M52S128168A ACTION Note Idle after tRFC (ABI) 6 Idle after tRFC (ABI) 6 ABI 7 ABI Publication Date: Oct. 2007 Revision: 1.1 ...

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... ESMT Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1 Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 30/47 ...

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... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M52S128168A Publication Date: Oct. 2007 Revision: 1.1 31/47 ...

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... The minimum of 200us after stable power and clock (CLK,CLK),apply NOP & take CKE high. 4. Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS.. Elite Semiconductor Memory Technology Inc M52S128168A ...

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... Row precharge. Last valid output will be Hi Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst) Elite Semiconductor Memory Technology Inc Precharge Row Active ( A - Bank ) ( A - Bank ) SHZ M52S128168A Write ( A - Bank ) : after the clock. Publication Date: Oct. 2007 Revision: 1 ...

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... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. before row precharge , will be written. RDL Publication Date: Oct. 2007 Revision: 1.1 M52S128168A 34/47 ...

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... Note can be don’t cared when RAS , CAS and WE are high at the clock high going edge interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 ...

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... To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data interrupt burst write by Row precharge , both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 ...

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... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note : 1. t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 37/47 ...

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... ESMT Read & Write cycle with Auto Precharge @ Burst Length = 4 *Note : 1. t should be controlled to meet minimum t CDL (In the case of Burst Length = 1 & 2) Elite Semiconductor Memory Technology Inc. before internal precharge start. RAS M52S128168A Publication Date: Oct. 2007 Revision: 1.1 38/47 ...

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... ESMT Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4 *Note : 1. DQM is needed to prevent bus contention Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 39/47 ...

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... But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycles”. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 40/47 ...

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... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52S128168A Publication Date: Oct. 2007 Revision: 1.1 41/47 ...

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... Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t 3. Can not violate minimum refresh specification. (64ms) Elite Semiconductor Memory Technology Inc. prior to Row active command. SS M52S128168A Publication Date: Oct. 2007 Revision: 1.1 42/47 ...

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... CKE going high to complete self refresh exit. RFC 7. Burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc. M52S128168A is required before exit from self refresh. RAS Publication Date: Oct. 2007 Revision: 1.1 ...

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... CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Extended Mode Register Set Cycle M52S128168A Publication Date: Oct. 2007 Revision: 1 ...

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... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 0.80 REF e 0.80 BSC Θ 0° 10° M52S128168A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- DETAIL "A" SECTION B-B Dimension in inch Min Norm Max ...

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... M52S128168A Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.315 0.319 0.315 0.319 0.252 0.252 0.031 Publication Date: Oct. 2007 Revision: 1.1 ...

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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52S128168A Publication Date: Oct. 2007 Revision: 1.1 47/47 ...