PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet
PIC24FJ256GA106-I/MR
Specifications of PIC24FJ256GA106-I/MR
Related parts for PIC24FJ256GA106-I/MR
PIC24FJ256GA106-I/MR Summary of contents
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... DA2/GB2/GA3 Families ..................................... 1 3.0 Device Programming – ICSP ............................ 14 4.0 Device Programming – Enhanced ICSP ........... 29 5.0 The Programming Executive ............................. 42 6.0 Device Details ................................................... 54 7.0 AC/DC Characteristics and Timing Requirements .................................................. 56 2010 Microchip Technology Inc. 2.0 PROGRAMMING OVERVIEW OF THE PIC24FJXXXDA1/DA2/ GB2/GA3 FAMILIES There are two ...
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... FIGURE 2-3: Regulator Enabled (V 3.3V C EFC (10 F typ) Figure 2-10 provide the pin diagrams CONNECTIONS FOR THE ON-CHIP REGULATOR ): DD PIC24FJXXXDA1/DA2/GB2 V DD ENVREG V CAP V SS CONNECTIONS FOR THE V PIN BAT tied Battery): BAT DD PIC24FJXXXGA3 BAT V CAP V SS 2010 Microchip Technology Inc. ...
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... BAT programming. FIGURE 2-4: PIN DIAGRAM (64-PIN TQFP) PGEC3/AN5/C1INA/V /RP18/CN7/RB5 BUSON PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 PGEC1/AN1/RP1/V PGED1/AN0/V +/RP0/ REF 2010 Microchip Technology Inc. During Programming Pin Description P Programming Enable I Enable for On-Chip Voltage Regulator P Power Supply P Ground P On-Chip Voltage Regulator Output to the Core ...
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... PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5 PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4 PGEC1/CV -/AN1/RP1/SEG6//CN3/RB1 REF PGED1/CV +/AN0/RP0/SEG7/PMA6/CN2/RB0 REF DS39970B-page 4 1 RE5 RE6 2 RE7 3 RG6 4 RG7 5 RG8 6 MCLR 7 RG9 8 PIC24FJXXXGA306 RB3 13 RB2 RC14 47 RC13 46 RD0 45 RD11 44 RD10 43 RD9 42 RD8 RC15 39 RC12 RG2 36 RG3 35 RF6 34 RF2 33 RF3 2010 Microchip Technology Inc. ...
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... PIC24FJXXXDA1/DA2/GB2/GA3 FIGURE 2-6: PIN DIAGRAM (64-PIN TQFP) PGEC3/AN5/RP18/V /C1INA/CN7/RB5 BUSON PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 PGEC1/AN1/RP1/V REF PGED1/AN0/RP0/V REF 2010 Microchip Technology Inc. 1 RE5 RE6 2 RE7 3 RG6 4 RG7 5 RG8 6 MCLR 7 PIC24FJXXXGB206 RG9 RB3 13 RB2 14 -/CN3/RB1 15 +/ CN2/RB0 16 48 RC14 47 RC13 46 RD0 45 RD11 44 RD10 43 RD9 42 RD8 ...
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... DS39970B-page 6 1 RE5 RE6 2 RE7 3 RC1 4 RC3 5 RG6 6 RG7 7 RG8 8 MCLR 9 RG9 10 PIC24FJXXXGA308 RE8 13 RE9 RB3 17 RB2 RC14 59 RC13 58 RD0 57 RD11 56 RD10 55 RD9 54 RD8 53 RA15 52 RA14 RC15 49 RC12 RG2 46 RG3 RF6 45 44 RF7 43 RP15 RF2 42 41 RF3 2010 Microchip Technology Inc. ...
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... PIC24FJXXXDA1/DA2/GB2/GA3 FIGURE 2-8: PIN DIAGRAM (100-PIN TQFP) PGEC3/AN5/RP18/V /C1INA/CN7/RB5 BUSON PGED3/AN4/C1INB/USBOEN// RP28/GD4/CN6/RB4 PGEC1/AN1/RP1/CN3/RB1 PGED1/AN0/RP0CN2/RB0 2010 Microchip Technology Inc. RG15 RE5 3 RE6 4 RE7 5 RC1 6 RC2 7 RC3 8 RC4 9 RG6 10 RG7 11 PIC24XJXXXDAX10 RG8 12 MCLR 13 RG9 RA0 17 RE8 18 RE9 RB3 22 RB2 RC14 74 RC13 73 RD0 ...
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... RE8 RE9 PGC3/AN5/C1INA/RP18/SEG2/CN7/RB5 PGD3/AN4/C1INB/RP28/SEG3/CN6/RB4 RB3 RB2 PGEC1/CV -/AN1/RB1/SEG6 REF PGED1/CV +/AN0/RB0/SEG7 REF DS39970B-page PIC24FJXXXGA310 RC14 74 RC13 73 RD0 72 RD11 71 RD10 70 RD9 69 RD8 68 RA15 67 RA14 RC15 64 RC12 RA5 61 RA4 60 RA3 59 RA2 58 RG2 57 RG3 56 RF6 55 RF7 54 RF8 53 RF2 52 RF3 51 2010 Microchip Technology Inc. ...
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... PIN DIAGRAM (100-PIN TQFP) RG15 V RE5 RE6 RE7 RC1 RC2 RC3 RC4 RG6 RG7 RG8 MCLR RG9 V V RA0 RE8 RE9 PGEC3/AN5/RP18/V / C1INA/CN7/RB5 BUSON PGED3/AN4/RP28/USBOEN/ C1INB/CN6/RB4 RB3 RB2 PGEC1/CV -/AV -/AN1/RP1/CN3/RB1 REF REF PGED1/CV -/AV -/AN0/RP0/CN2/RB0 REF REF 2010 Microchip Technology Inc PIC24XJXXXGB210 RC14 74 RC13 ...
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... RF2 RD14 RF4 RF5 RD12 RD2 GD1 RD3 V RC14 SS V RC13 RD11 DD RD0 N/C RD10 RD8 RD10 RA14 RC12 V RC15 SS RA5 RA3 RA4 V D+/RG2 RA2 USB N/C RF8 D-/RG3 RD15 RF3 RF2 RD14 RF4 RF5 2010 Microchip Technology Inc. ...
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... RG8 RG9 G RE8 RE9 H RB5/ RB4/ PGEC3 PGED3 J RB3 RB2 RB7/ PGED2 K RB1/ RB0/ RA10 PGEC1 PGED1 L RB6/ RA9 AV PGEC2 2010 Microchip Technology Inc RE0 RG0 RF1 V N/C BAT RE2 RE1 RA7 RF0 V / RD5 CAP V DDCORE RG14 RA6 N/C RD7 ...
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... PIC24FJXXXDA1/DA2/GB2/GA3 family variants. Configuration Word Addresses Write Erase Blocks Blocks 1 2 344 43 00ABFEh 00ABFCh 00ABFAh 688 86 0157FEh 0157FCh 1368 171 02ABFEh 02ABFCh 02ABFAh Table 2-2. Section 6 00ABF8h 0157FAh 0157F8h 02ABF8h 2010 Microchip Technology Inc. ...
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... PIC24FJXXXDA1/DA2/GB2/GA3 FIGURE 2-14: PROGRAM MEMORY MAP Note 1: The size and address boundaries for user Flash code memory are device dependent. See 2010 Microchip Technology Inc. 000000h User Flash (1) Code Memory (1) 0XXXF7h (1) 0XXXF8h Flash Configuration Words (1) 0XXXFEh (1) 0XXX00h Reserved 7FFFFEh 800000h ...
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... REGOUT Shift out the VISI 0001 (0784h) register. N/A Reserved. 0010-1111 FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ Perform Chip Erase Program Memory Verify Program Program Configuration Bits Verify Configuration Bits Exit ICSP End 2010 Microchip Technology Inc. ...
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... A CPU stall occurs when an instruction modifies a register that is used for indirect addressing by the following instruction. 2010 Microchip Technology Inc. Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGECx clocks are needed on start-up, resulting in a 9-bit SIX command instead of the normal 4-bit SIX command ...
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... PGECx. For all Significant bit (LSb) is transmitted first ... LSb Shift Out VISI Register<15:0> PGEDx = Output PIC24FJXXXDA1/DA2/GB2/GA3 data transmissions, the Least P4A 13 14 MSb Execution Takes Place, Fetch Next Control Code PGEDx = Input 2010 Microchip Technology Inc. ...
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... PGECx P18 2010 Microchip Technology Inc. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 4D434851h in hexa- decimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first ...
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... PGEDx pins (see Figure 3-2). Note: Program memory must be erased before writing any data to program memory. FIGURE 3-5: CHIP ERASE FLOW Start Write 404Fh to NVMCON SFR Set the WR bit to Initiate Erase bit cleared (‘ 0 ’)? Yes End 2010 Microchip Technology Inc. ...
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... MOV 0000 883C22 MOV 0000 000000 NOP 0001 <VISI> Clock out contents of the VISI register 0000 000000 NOP 2010 Microchip Technology Inc. Description 0x200 #0x404F, W10 W10, NVMCON #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0,[W0] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI DS39970B-page 19 ...
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... Steps 3-9 are repeated until all of the code memory is programmed. FIGURE 3- MSB1 MSB3 W5 Description 0x200 #0x4001, W10 W10, NVMCON #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 PACKED INSTRUCTION WORDS IN W0: LSW0 MSB0 LSW1 LSW2 MSB2 LSW3 2010 Microchip Technology Inc. ...
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... Clock out contents of the VISI register. 0000 000000 NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 3 through 9 until all code memory is programmed. 2010 Microchip Technology Inc. Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200 ...
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... PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 DS39970B-page 22 Start LoopCount = 0 Configure Device for Writes Load 1 Instruction Word Write Buffer at <Addr> All No instruction words written? Yes Start Write Sequence and Poll for WR bit to be Cleared All No locations done? Yes End 2010 Microchip Technology Inc. ...
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... CW2 Last Word – 4 CW3 Last Word – 6 CW4 2010 Microchip Technology Inc. Table 3-7 provides the ICSP programming details for programming the Configuration Word locations, includ- ing the serial pattern with the ICSP command code, which must be transmitted, LSb first, using the PGECx and PGEDx pins (see In Step 1, the Reset vector is exited ...
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... GOTO 0000 000000 NOP Step 10: Repeat Steps 5 through 9 to write Configuration Word 2 to Configuration Word 4. DS39970B-page 24 Description 0x200 #<CW1Address15:0>, W7 #0x4003, W10 W10, NVMCON #<CW1Address23:16>, W0 W0, TBLPAG #<CW1_VALUE>, W6 #0x0000, W8 NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200 2010 Microchip Technology Inc. ...
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... NOP Step 6: Repeat Steps 3 through 5 until all desired code memory is read (note that “Reset device internal PC” will be Step 5). 2010 Microchip Technology Inc. To minimize the reading time, the packed instruction word format that was utilized for writing is also used for ...
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... Configuration Words. Note that the TBLPAG register must be loaded with 00h for 64 Kbytes, and 01h for 128 and 256 Kbytes devices initialized to the lower 16 bits of the Configuration Word location. Description 0x200 #<CW1Address23:16>, W0 W0, TBLPAG #<CW1Address15:0>, W6 #VISI, W7 0x200 2010 Microchip Technology Inc. ...
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... All No code memory verified? Yes End 2010 Microchip Technology Inc. 3.11 Reading the Application ID Word The Application ID Word is stored at address, 8007F0h, in executive code memory. To read this memory location, you must use the SIX control code to move this program memory location to the VISI register ...
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... TBLRDL [W0], [W1] 0000 000000 NOP 0000 000000 NOP Step 3: Output the VISI register using the REGOUT command. 0001 <VISI> Clock out contents of the VISI register 0000 000000 NOP DS39970B-page 28 Description 0x200 #0x80, W0 W0, TBLPAG #0x07F0, W0 #VISI, W1 2010 Microchip Technology Inc. ...
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... Next, the device is erased. Then, the code memory is programmed, followed by the configuration locations. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. 2010 Microchip Technology Inc. After the programming executive has been verified in memory (or PIC24FJXXXDA1/DA2/GB2/GA3 ...
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... While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state Program/Verify Entry Code = 4D434850h ... b31 b30 b29 b28 b27 b3 P1A P1B Figure 4-3, entering Enhanced ICSP , the case After must be IH P19 2010 Microchip Technology Inc. ...
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... On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed. 2010 Microchip Technology Inc. FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY Start ...
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... WDT prescaler ratio of 1:32 General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space the descriptions for the + on RA9 and RA10) REF + on RB0 and RB1) REF REF 2010 Microchip Technology Inc. ...
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... The JTAGEN bit can be modified using only In-Circuit Serial Programming™ (ICSP™). 3: Irrespective of the WPCFG status, if WPEND = WPFP corresponds to the Configuration Words page, the Configuration Words page will be protected 2010 Microchip Technology Inc. (1) Description General Segment Code Flash Write Protection bit ...
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... First address of designated code page is the lower boundary of the segment; the last implemented page will be the last write-protected page. If WPEND = 0: Last address of designated code page is the upper boundary of the segment Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use (3) 2010 Microchip Technology Inc. ...
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... Configuration Words would be interpreted as a NOP opcode. 2: The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). 3: Irrespective of the WPCFG status, if WPEND = WPFP corresponds to the Configuration Words page, the Configuration Words page will be protected 2010 Microchip Technology Inc. for the (1) Description /CV ...
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... Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary (XT, HS, EC) Oscillator 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC (FRC) Oscillator 2010 Microchip Technology Inc. ...
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... The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). 3: Irrespective of the WPCFG status, if WPEND = WPFP corresponds to the Configuration Words page, the Configuration Words page will be protected 2010 Microchip Technology Inc. (1) Description 11 = Watchdog Timer is enabled in hardware 10 = Watchdog Timer is controlled with the SWDTEN bit setting 01 = Watchdog Timer is enabled only while device is active and disabled in Sleep ...
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... Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP<6:0> Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP<6:0> BAT BAT (3) 2010 Microchip Technology Inc. ...
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... The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™). 3: Irrespective of the WPCFG status, if WPEND = WPFP corresponds to the Configuration Words page, the Configuration Words page will be protected 2010 Microchip Technology Inc. (1) Description Write-Protect Program Flash Pages (valid when WPDIS = 0) ...
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... READP command reads back the programmed Configuration bits and verifies that the programming was successful. Section 4.6.4 for Start ConfigAddress = 0XXXF8h Send PROGW Command Is PROGP response PASS? Yes Is No ConfigAddress (1) 0XXXFEh? Yes End (1) No Failure Report Error 2010 Microchip Technology Inc. ...
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... PIC24FJXXXDA1/DA2/GB2/GA3 devices can be located by the user anywhere in the program space, and configured in a wide range of sizes. 2010 Microchip Technology Inc. Code segment protection provides an added level of protection to a designated area of program memory by disabling the NVM safety interlock, whenever a write or erase address falls, within a specified range ...
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... MHz. To ensure that the programmer does not clock too fast recommended that a 4 MHz clock be provided by the programmer LSb PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE ... LSb Figure 5-3 for this protocol. 2010 Microchip Technology Inc. ...
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... The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. 2010 Microchip Technology Inc. to the programmer. Since the programming executive has no time-out imperative that the programmer correctly follow the described communication protocol. ...
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... This command is reserved; it will return a NACK Program one instruction word of code memory at the specified address and then verify. TBD Query if the code memory is blank. Table 2-2 executive will “NACK” all Section 5.3.1.3 “QE_Code Description (1) for device-specific information. 2010 Microchip Technology Inc. ...
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... This command is used as a “Sanity Check” to verify that the programming executive is operational. Expected Response (2 words): 1000h 0002h Note: This instruction is not required for programming development purposes only. 2010 Microchip Technology Inc. 5.2.6 READC COMMAND Opcode 0 Field Opcode Length N Addr_MSB ...
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... Device ID register located at the specified memory address. After the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 Words): 1400h 0002h 2010 Microchip Technology Inc. 0 Length Addr_MSB Description ...
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... After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 Words): 1500h 0002h Note: Refer to Table 2-2 for code memory size information. 2010 Microchip Technology Inc. 5.2.10 PROGW COMMAND Opcode Data_MSB Field Opcode Dh ...
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... QE_Code using a single byte with the following format: main version in upper nibble and revision in the lower nibble (i.e., 23h means Version 2.3 of programming executive software). Expected Response (2 Words): 1BMNh (where “MN” stands for Version M.N) 0002h 2010 Microchip Technology Inc. 0 Length Description ...
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... D_1 First 16-bit data word (if applicable) D_N Last 16-bit data word (if applicable) 2010 Microchip Technology Inc. 5.3.1.1 Opcode Field The opcode is a 4-bit field in the first word of the response. The opcode indicates how the command was processed (see processed successfully, the response opcode is PASS ...
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... READP command 1)/ words. When reading an even number of program memory words (N even), the response to the READP command N words. QE_Code FOR NON-QUERY COMMANDS Description No error Verify failed Other error word format described in Format”. When reading 2010 Microchip Technology Inc. ...
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... EB0380 CLR 0000 000000 NOP 2010 Microchip Technology Inc. Storing the programming executive to executive memory is similar to normal programming of code memory. Namely, the executive memory must be erased and then the programming executive must be programmed, 64 words at a time. this control flow. ...
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... Clock out contents of the VISI register. 0000 000000 NOP Step 13: Reset the device internal PC. 0000 040200 GOTO 0000 000000 NOP DS39970B-page 52 Description #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3> [W6++], [W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] NVMCON, #15 0x200 NVMCON, W2 W2, VISI 0x200 2010 Microchip Technology Inc. ...
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... GOTO 0000 000000 NOP Step 6: Repeat Steps 4 and 5 until all 1024 instruction words of executive memory are read. 2010 Microchip Technology Inc. Description Reading the contents of executive memory can be performed using the same technique described in has been Section 3.8 “Reading Code ...
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... DEVICE IDs DEVID 4109 410D 410B 410F 4108 410C 410A 410E 46C0 46C4 46C8 46C2 46C6 46CA 4100 4104 4102 4106 DEV<7:0> REV<3:0> 2010 Microchip Technology Inc. ...
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... Configuration Block (masked) byte sum of ((CW1 & 0x7FFF) + (CW2 & 0xFFFF) + (CW3 & 0xFFFF) + (CW4 & 0xFFFF)) Note: CW1 address is the last location of implemented program memory; CW2 is (last location – 2); CW3 is (last location – 4); CW4 is (last location – 6). 2010 Microchip Technology Inc. Erased Checksum Computation Checksum Value ...
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... meet AC specifications F Required for controller core ns ICSP™ mode ns Enhanced ICSP mode ns ICSP mode ns Enhanced ICSP mode ns ICSP mode ns Enhanced ICSP mode s µs ns should always be within ±0. the nominal DD 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. 08/04/10 ...
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... Device Overview 1 Programming Overview of the PIC24FJXXXDA1/DA2/GB2/ GA3 Families 1 Device Programming – ICSP 14 Device Programming – Enhanced ICSP 29 The Programming Executive 42 Device Details 54 AC/DC Characteristics and Timing Requirements 56 2010 Microchip Technology Inc. PIC24FJXXXDA1/DA2/GB2/GA3 DS39970B-page 1 ...