PIC24FJ256GA106-I/MR Microchip Technology, PIC24FJ256GA106-I/MR Datasheet - Page 37

• Manufacturer Part Number: PIC24FJ256GA106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Number Of I /o: 53
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-3:
 2010 Microchip Technology Inc.
FWDTEN<1:0>
FWPSA
GCP
GWRP
ICS<1:0>
IESO
IOL1WAY
JTAGEN
LPCFG
OSCIOFCN
POSCMD<1:0>
Note 1:
2:
3:
Bit Field
(2)
Bits<23:16> should be programmed to a value of 0x00 to ensure that accidental program execution of any
of the Configuration Words would be interpreted as a NOP opcode.
The JTAGEN bit can be modified only using In-Circuit Serial Programming™ (ICSP™).
Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words
page, the Configuration Words page will be protected
PIC24FJXXXGA3 CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
CW1<6:5>
CW1<9:8>
CW2<1:0>
CW1<13>
CW1<12>
CW2<15>
CW1<14>
CW1<10>
CW1<4>
CW2<4>
CW2<5>
PIC24FJXXXDA1/DA2/GB2/GA3
(1)
11 = Watchdog Timer is enabled in hardware
10 = Watchdog Timer is controlled with the SWDTEN bit setting
01 = Watchdog Timer is enabled only while device is active and disabled
00 = Watchdog Timer is disabled in hardware; SWDTEN bit is disabled
Watchdog Timer Prescaler Ratio Select bit
1 = Watchdog Timer prescaler ratio of 1:128
0 = Watchdog Timer prescaler ratio of 1:32
General Segment Program Memory Code Protection bit
1 = Code protection is disabled
0 = Code protection is enabled for the entire program memory space
General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
ICD Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
10 = Emulator functions are shared with PGEC2/PGED2
01 = Emulator functions are shared with PGEC3/PGED3
00 = Reserved; do not use
Internal External Switchover bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock
0 = The IOLOCK is cleared as needed (provided an unlocking sequence
JTAG Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
Low-Power Regulator Control Enable bit
0 = LP regulator feature is available and controlled by ULPEN during
1 = LP regulator feature is not available
OSC2 Pin Function bit (except in XT and HS modes)
If POSCMD<1:0> = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (F
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD<1:0> = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
sequence has been completed. Once set, the Peripheral Pin
Select (PPS) registers cannot be written to a second time.
is executed)
Sleep
in Sleep; SWDTEN bit is disabled
Description
OSC
/2)
DS39970B-page 37