COP8SGR728M8 National Semiconductor, COP8SGR728M8 Datasheet - Page 37

• Manufacturer Part Number: COP8SGR728M8
• Description: 8-Bit Microcontroller IC
• Manufacturer: National Semiconductor
• Series: COP8r

Specifications of COP8SGR728M8

• Controller Family/series: COP8
• Core Size: 8 Bit
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package: 28SOIC W
• Family Name: COP8
• Maximum Speed: 15 MHz
• Ram Size: 512 Byte
• Program Memory Size: 32 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: USART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.0 Interrupts
10.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active
interrupt is software trap, than E0 is generated. This number
replaces the lower byte of the PC. The upper byte of the PC
(Continued)
FIGURE 26. VIS Operation
37
remains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration
ranking. This vector is read from program memory and
placed into the PC which is now pointed to the 1st instruction
of the service routine of the active interrupt with the highest
arbitration ranking.
Figure 26 illustrates the different steps performed by the VIS
instruction. Figure 27 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
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