COP8SGR728M8 National Semiconductor, COP8SGR728M8 Datasheet - Page 52

• Manufacturer Part Number: COP8SGR728M8
• Description: 8-Bit Microcontroller IC
• Manufacturer: National Semiconductor
• Series: COP8r

Specifications of COP8SGR728M8

• Controller Family/series: COP8
• Core Size: 8 Bit
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package: 28SOIC W
• Family Name: COP8
• Maximum Speed: 15 MHz
• Ram Size: 512 Byte
• Program Memory Size: 32 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: USART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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14.0 Instruction Set
14.7 INSTRUCTION EXECUTION TIME
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
Note 18: =
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
>
X A, (Note 18)
LD A, (Note 18)
LD B, Imm
LD B, Imm
LD Mem, Imm
LD Reg, Imm
IFEQ MD, Imm
Memory location addressed by B or X or directly.
RPND
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
[B]
1/1
1/1
2/2
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3
3/4
3/4
3/4
(Continued)
Register
1/1
Indirect
[X]
1/3
1/3
Immed.
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
Direct
2/3
2/3
3/3
2/3
3/3
Immed.
2/2
1/1
2/2
52
Instructions Using A & C
Transfer of Control Instructions
Memory Transfer Instructions
[B+, B−]
Auto Incr. & Decr.
1/2
1/2
2/2
Register Indirect
CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
JMPL
JMP
JP
JSRL
JSR
JID
VIS
RET
RETSK
RETI
INTR
NOP
[X+, X−]
1/3
1/3
(If B
(If B
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
3/4
2/3
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
<
>
16)
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