CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 10

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

3.2 Control
10
SYMBOL
MODE
MCLK
LQFP
10
11
FBGA
E1
E2
TYPE
I
I
Master Clock Input
This pin is a free running reference clock that should be
either 1.544 MHz for T1/J1 or 2.048 MHz for E1 operation.
This timing reference is used as follows:
- Timing reference for the clock recovery and jitter attenua-
tion circuitry.
- RCLK reference during Loss of Signal (LOS) conditions
- Transmit clock reference during Transmit all Ones (TAOS)
condition
- Wait state timing for microprocessor interface
- When this pin is held “High”, the PLL clock recovery cir-
cuit is disabled. In this mode, the CS61884 receivers
function as simple data slicers.
- When this pin is held “Low”, the receiver paths are pow-
ered down and the output pins RCLK, RPOS, and RNEG
are High-Z.
Mode Select
This pin is used to select whether the CS61884 operates in
Serial host, Parallel host or Hardware mode.
Host Mode - The CS61884 is controlled through either a
serial or a parallel microprocessor interface (Refer to
MODE
Hardware Mode - The microprocessor interface is disabled
and the device control/status are provided through the pins
on the device.
NOTE: For serial host mode connect this pin to a resistor
(See Section 13 on page 32).
divider consisting of two 10KΩ resistors between
VCCIO and GNDIO.
Table 1. Operation Mode Selection
Pin State
VCCIO/2
HIGH
LOW
DESCRIPTION
OPERATING Mode
Parallel Host Mode
Serial Host Mode
Hardware Mode
CS61884
DS485F1
HOST