CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 11

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

DS485F1
RDY/ACK/SDO
MUX/BITSEN0
SYMBOL
INT
LQFP
43
82
83
FBGA
K13
K14
K2
TYPE
O
O
I
Multiplexed Interface/Bits Clock Select
Host Mode -This pin configures the microprocessor inter-
face for multiplexed or non-multiplexed operation.
Hardware mode - This pin is used to enable channel 0 as
a G.703 BITS Clock recovery channel (Refer to
INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE
(See Section 8 on page 23). Channel 1 through 7 are not
affected by this pin during hardware mode. During host
mode the G.703 BITS Clock recovery function is enabled by
the
on page 41).
NOTE: The MUX pin only controls the BITS Clock function in
Interrupt Output
This active low output signals the host processor when one
of the CS61884’s internal status register bits has changed
state. When the status register is read, the interrupt is
cleared. The various status changes that would force INT
active are maskable via internal interrupt enable registers.
NOTE: This pin is an open drain output and requires a 10 kΩ
Data Transfer Acknowledge/Ready/Serial Data Output
Intel Parallel Host Mode - During a read or write register
access, RDY is asserted “Low” to acknowledge that the de-
vice has been accessed. An asserted “High” acknowledges
that data has been written or read. Upon completion of the
bus cycle, this pin High-Z.
Motorola Parallel Host Mode - During a data bus read
operation this pin “ACK” is asserted “High” to indicate that
data on the bus is valid. An asserted “Low” on this pin dur-
ing a write operation acknowledges that a data transfer to
the addressed register has been accepted. Upon comple-
tion of the bus cycle, this pin High-Z.
NOTE: Wait state generation via RDY/ACK is disabled in
RZ mode (No Clock Recovery).
Serial Host Mode - When the microprocessor interface is
configured for serial bus operation, “SDO” is used as a seri-
al data output. This pin is forced into a high impedance
state during a serial write access. The CLKE pin controls
whether SDO is valid on the rising or falling edge of SCLK.
Upon completion of the bus cycle, this pin High-Z.
Hardware Mode - This pin is not used and should be left
open.
Bits Clock Enable Register (1Eh)
Pin State
HIGH
LOW
Hardware Mode
pull-up resistor.
Table 2. Mux/Bits Clock Selection
Parallel Host Mode
non multiplexed
multiplexed
DESCRIPTION
Hardware Mode
BITS Clock OFF
(See Section 14.31
BITS Clock ON
CS61884
BUILDING
11