CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 38

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

14.16 Global Control Register (0Fh)
14.17 Line Length Channel ID Register (10h)
38
[1:0]
[7:3]
[2:0]
BIT
BIT
[7]
[6]
[5]
[4]
[3]
[2]
JASEL [1:0]
AWG Auto-
Increment
RSVD 7-3
LENGTH
LLID 2-0
RAISEN
CODEN
NAME
NAME
RSVD
JACF
FIFO
This register is the global control for the AWG Auto-Increment, Automatic AIS insertion,
encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for
all eight channels. Register bits default to 00h after power-up or reset.
The AWG Auto-Increment bit indicates whether to auto-increment the
Register (17h)
the phase samples address portion of the address register increments after each read or
write access. This bit must be set before any bit in the AWG Enable register is set, if this
function is required.
On LOS, this bit controls the automatic AIS insertion into all eight receiver paths.
Line encoding/decoding Selection
Jitter Attenuator FIFO length Selection
Jitter Attenuator Corner Frequency Selection
These bits select the position of the Jitter Attenuator.
The value written to these bits specify the LIU channel for which the Pulse Shape Configura-
tion Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs
will select channel 0. The pulse shape configuration data for the channel specified in this reg-
ister are written or read through the Line Length Data Register (11h). Register bits default
to 00h after power-up or reset.
0 = Disabled
1 = Enabled
0 = B8ZS/HDB3 (T1/J1/E1 respectively)
0 = 32 bits
1 = 64 bits
0 = 1.25Hz
1 = 2.50Hz
1 = AMI
JASEL 1 JASEL 0
E1
0
0
1
1
(See Section 14.24 on page 40) after each access. Thus, when this bit is set,
0
1
0
1
3.78Hz
7.56Hz
T1/J1
RESERVED (These bits must be set to 0.)
RESERVED (This bit must be set to 0.)
Transmit Path
Receive Path
POSITION
Disabled
Disabled
Description
Description
AWG Phase Address
CS61884
DS485F1