CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 44

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

channel or channels. To enable the AWG function
for a specific channel or channels the correspond-
ing bit(s) in the
Section 14.26 on page 40) must be set to “1”. When
the corresponding bit(s) in the AWG Enable Regis-
ter are set to “0” pre-programmed pulse shapes are
selected for transmission.
In order to access and write data for a customized
pulse shape to a specific channel or channels, the
following steps are required. First the desired chan-
nel and phase sample addresses must be written to
the
14.25 on page 40). Once the channel and phase
sample address have been selected, the actual phase
sample data may be entered into the AWG Phase
Data Register at the selected phase sample address
selected by the lower five bits of the
Address Register (17h)
page 40)).
To change the phase sample address of the selected
channel the user may use either of the following
steps. First, the user can re-write the phase sample
address to the AWG Phase Address Register or set
the Auto-Increment bit (Bit 7) in the
trol Register (0Fh)
page 38)) to “1”. When this bit is set to “1” only the
first phase sample address (00000 binary) needs to
be written to the
(17h)
subsequent access (read or write) to the
Phase Data Register (18h)
page 40) will automatically increment the phase
sample address. The channel address, however, re-
mains unaffected by the Auto-Increment mode.
Since the number of phase samples forming the
customized pulse shape varies with the mode of op-
eration (E1/T1/J1), the
ister (17h)
be re-written in order to re-start the phase sample
address sequence from zero.
44
AWG Phase Data Register (18h)
(See Section 14.24 on page 40), and each
(See Section 14.24 on page 40) needs to
AWG Enable Register (19h)
AWG Phase Address Register
AWG Phase Address Reg-
(See Section 14.16 on
(See Section 14.24 on
(See Section 14.25 on
AWG Phase
Global Con-
(See Section
AWG
(See
The AWG Broadcast function allows the same data
to be written to different channels simultaneously.
This is done with the use of the
Register (16h)
each bit in the AWG Broadcast Register corre-
sponds to a different channel (bit 0 is channel 0, and
bit 3 is channel 3 & etc.).
To write the same pulse shaping data to multiple
channels, simple set the corresponding bit to “1” in
the
14.23 on page 40). This function only requires that
one of the eight channel addresses be written to the
AWG Phase Address Register (17h)
14.24 on page 40). During an AWG read sequence,
the bits in the AWG Broadcast Register are ig-
nored. During an AWG write sequence, the select-
ed channel or channels are specified by both the
channel address specified by the upper bits of the
AWG Phase Address Register (17h)
14.24 on page 40) and the selected channel or chan-
nels in the
Section 14.23 on page 40).
During a multiple channel write the first channel
that is written to, is the channel that was address by
the AWG Phase Address Register. This channel’s
bit in the AWG Broadcast Register can be set to ei-
ther “1” or “0”. For a more descriptive explanation
of how to use the AWG refer to the “How To Use
The CS61880/CS61884 Arbitrary Waveform Gen-
erator” application note AN204.
AWG Broadcast Register (16h)
AWG Broadcast Register (16h)
(See Section 14.23 on page 40)),
AWG Broadcast
CS61884
(See Section
(See Section
(See Section
DS485F1
(See