PIC16F610-E/ML Microchip Technology, PIC16F610-E/ML Datasheet
PIC16F610-E/ML
Specifications of PIC16F610-E/ML
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PIC16F610-E/ML Summary of contents
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... Microchip Technology Inc. PIC16F610/16HV610 PIC16F616/16HV616 Data Sheet 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41288F ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Precision Internal Oscillator: - Factory calibrated to ±1%, typical - User selectable frequency: 4 MHz or 8 MHz • Power-Saving Sleep mode • Voltage Range: - PIC16F610/616: 2.0V to 5.5V - PIC16HV610/616: 2.0V to user defined maximum (see note) • Industrial and Extended Temperature Range • Power-on Reset (POR) • ...
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... PIC16F610/616/16HV610/616 Program Memory Data Memory Device Flash SRAM (bytes) (words) PIC16F610 1024 PIC16HV610 1024 PIC16F616 2048 PIC16HV616 2048 PIC16F610/16HV610 14-Pin Diagram (PDIP, SOIC, TSSOP RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V PP RC5 RC4/C2OUT RC3/C12IN3- TABLE 1: PIC16F610/16HV610 I/O Pin Comparators RA0 13 C1IN+ RA1 12 C12IN0- RA2 11 C1OUT ...
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... AN7 C12IN3- RC4 6 — C2OUT RC5 5 — — — 1 — — — 14 — — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 RA0/AN0/C1IN+/ICSPDAT 2 13 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT 4 10 RC0/AN4/C2IN RC1/AN5/C12IN1 RC2/AN6/C12IN2-/P1D 7 14- ...
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... PIC16F610/616/16HV610/616 PIC16F610/16HV610 16-Pin Diagram (QFN) RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/V PP RC5 TABLE 3: PIC16F610/16HV610 I/O Pin Comparators RA0 12 C1IN+ RA1 11 C12IN0- RA2 10 C1OUT (1) RA3 3 — RA4 2 — RA5 1 — RC0 9 C2IN+ RC1 8 C12IN1- RC2 7 C12IN2- RC3 6 C12IN3- RC4 5 C2OUT RC5 4 — — 16 — — ...
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... C2OUT RC5 4 — — — 16 — — — 13 — — Note 1: Input only. 2: Only when pin is configured for external MCLR. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 RA0/AN0/C1IN+/ICSPDAT 12 1 RA1/AN1/C12IN0-/ PIC16F616/ PIC16HV616 RA2/AN2/T0CKI/INT/C1OUT 10 3 RC0/AN4/C2IN1 16- PIN SUMMARY Timers CCP Interrupts Pull-ups — ...
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... PIC16F610/616/16HV610/616 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................ 13 3.0 Oscillator Module ....................................................................................................................................................................... 27 4.0 I/O Ports .................................................................................................................................................................................... 33 5.0 Timer0 Module .......................................................................................................................................................................... 45 6.0 Timer1 Module with Gate Control .............................................................................................................................................. 49 7.0 Timer2 Module (PIC16F616/16HV616 only) ............................................................................................................................. 55 8.0 Comparator Module ................................................................................................................................................................... 57 9.0 Analog-to-Digital Converter (ADC) Module (PIC16F616/16HV616 only) .................................................................................. 73 10.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC16F616/16HV616 Only) .................. 85 11 ...
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... DEVICE OVERVIEW The PIC16F610/616/16HV610/616 is covered by this data sheet available in 14-pin PDIP, SOIC, TSSOP and 16-pin QFN packages. Block Diagrams and pinout descriptions of the devices are as follows: • PIC16F610/16HV610 (Figure 1-1, Table 1-1) • PIC16F616/16HV616 (Figure 1-2, Table 1-2) FIGURE 1-1: ...
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... PIC16F610/616/16HV610/616 FIGURE 1-2: PIC16F616/16HV616 BLOCK DIAGRAM Configuration Flash Program Memory Program 14 Bus Instruction Reg 8 Instruction Decode and Control Timing OSC1/CLKIN Generation OSC2/CLKOUT Internal Oscillator Block T1G T1CKI Timer0 T0CKI Analog-To-Digital Converter DS41288F-page 10 INT 13 Data Bus Program Counter RAM 8-Level Stack 128 Bytes ...
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... TABLE 1-1: PIC16F610/16HV610 PINOUT DESCRIPTION Name Function RA0/C1IN+/ICSPDAT RA1/C12IN0-/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR/V PP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/C2IN+ RC1/C12IN1- RC2/C12IN2- RC3/C12IN3- RC4/C2OUT RC5 Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Input Output Type ...
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... PIC16F610/616/16HV610/616 TABLE 1-2: PIC16F616/16HV616 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT RA1/AN1/C12IN0-/V /ICSPCLK REF RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/V PP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D RC3/AN7/C12IN3-/P1C RC4/C2OUT/P1B RC5/CCP1/P1A Legend Analog input or output ST = Schmitt Trigger input with CMOS levels TTL DS41288F-page 12 Input Output Type Type ...
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... PIC16F610/16HV610 and the first (0000h-07FFh) for the PIC16F616/16HV616 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first space (PIC16F610/16HV610) and space (PIC16F616/16HV616). The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). ...
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... Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of PIC16F610/16HV610 Register locations 40h-7Fh in Bank 0 are General Purpose Registers, implemented as static RAM. PIC16F616/16HV616 locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static RAM ...
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... FIGURE 2-3: DATA MEMORY MAP OF THE PIC16F610/16HV610 File Address (1) Indirect Addr. Indirect Addr. 00h TMR0 OPTION_REG 01h PCL 02h PCL STATUS STATUS 03h FSR FSR 04h PORTA TRISA 05h 06h PORTC TRISC 07h 08h 09h PCLATH PCLATH 0Ah INTCON INTCON 0Bh ...
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... PIC16F610/616/16HV610/616 TABLE 2-1: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... TABLE 2-2: PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte (1) (1) 83h ...
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... Status bits, see the Section 13.0 “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not PIC16F610/616/16HV610/616 should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction ...
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... Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ of the OPTION register. See Section 5.1.3 “Software Programmable Prescaler”. R/W-1 ...
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... PIC16F610/616/16HV610/616 2.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 GIE ...
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... TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed Note 1: PIC16F616/16HV616 only. PIC16F610/16HV610 unimplemented, read as ‘0’. DS41288F-page 22 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Reads as ‘0’ if Brown-out Reset is disabled. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ...
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... Table Read” (DS00556). DS41288F-page 24 2.3.2 STACK The PIC16F610/616/16HV610/616 Family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC16F610/16HV610 Direct Addressing (1) RP1 RP0 6 From Opcode Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-3. Unimplemented data memory locations, read as ‘0’. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 26 © 2009 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator INTOSC 8 MHz © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... PIC16F610/616/16HV610/616 3.2 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator mod- ules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. ...
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... The value of R varies with the Oscillator mode F selected (typically between 2 MΩ MΩ). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application ...
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... PIC16F610/616/16HV610/616 3.3.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4 ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. When the OSCTUNE register is modified, the frequency will begin shifting to the new frequency ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 32 © 2009 Microchip Technology Inc. ...
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... TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs ...
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... PIC16F610/616/16HV610/616 4.2 Additional Pin Functions Every PORTA pin on the PIC16F610/616/16HV610/ 616 has an interrupt-on-change option and a weak pull- up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘ ...
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... Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-1 U-0 R/W-1 WPUA4 — WPUA2 U = Unimplemented bit, read as ‘0’ ...
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... PIC16F610/616/16HV610/616 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. ...
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... IOAC RD IOAC ( Interrupt-on- From other Change R RA<5:3, 1:0> pins Write ‘0’ to RAIF Note 1: Comparator mode and ANSEL determines Analog Input mode. 2: Set has priority over Reset. 3: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Analog Input Mode C1OE Enable C1OE ...
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... PIC16F610/616/16HV610/616 4.2.4.4 RA3/MCLR/V PP Figure 4-3 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up • High Voltage Programming voltage input FIGURE 4-3: BLOCK DIAGRAM OF RA3 ...
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... Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable. 2: With CLKOUT option. 3: Analog Input mode comes from ANSEL. 4: Set has priority over Reset. 5: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 • a Timer1 gate (count enable) • a crystal/resonator connection • a clock output Note 1: PIC16F616/16HV616 only. Analog ...
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... PIC16F610/616/16HV610/616 4.2.4.6 RA5/T1CKI/OSC1/CLKIN Figure 4-5 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: FIGURE 4-5: BLOCK DIAGRAM OF RA5 ( Interrupt-on- Change R Write ‘0’ to RAIF Note 1: Timer1 LP Oscillator enabled. 2: Set has priority over Reset. DS41288F-page 40 • a general purpose I/O • ...
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... TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: For PIC16F616/HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 (1) (1) ANS4 ANS3 ANS2 ANS1 C1POL — ...
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... PIC16F610/616/16HV610/616 4.3 PORTC and the TRISC Registers PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D Converter (ADC) or Comparator. For specific information about individual functions such as the Enhanced CCP or the ADC, refer to the appropriate section in this data sheet ...
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... PORTC To Comparators To A/D Converter Note 1: Analog Input mode comes from ANSEL or Comparator mode. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 4.3.3 RC2/AN6 The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • an analog input to Comparators C1 and C2 • ...
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... PIC16F610/616/16HV610/616 (1) 4.3.5 RC4/C2OUT/P1B The RC4 is configurable to function as one of the following: • a general purpose I/O • a digital output from Comparator C2 • a digital output from the Enhanced CCP Note 1: PIC16F616/16HV616 only. 2: Enabling both C2OUT and P1B will cause a conflict on RC4 and create unpredictable results ...
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... Timer Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in the Configuration Word register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. ...
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... PIC16F610/616/16HV610/616 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...
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... TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 48 © 2009 Microchip Technology Inc. ...
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... ST Buffer is low power type when using LP osc, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter ...
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... PIC16F610/616/16HV610/616 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples determined by the Timer1 prescaler. CY 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. ...
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... Base (PIC16F616/16HV616 Only) The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 In Capture mode, the value in the TMR1H:TMR1L web site register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. ...
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... PIC16F610/616/16HV610/616 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 53 ...
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... PIC16F610/616/16HV610/616 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 CM2CON0 C2ON C2OUT C2OE CM2CON1 MC1OUT MC2OUT — INTCON GIE PEIE T0IE (1) PIE1 — ADIE CCP1IE (1) PIR1 — ADIF CCP1IF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...
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... T2CKPS<1:0> © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... PIC16F610/616/16HV610/616 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...
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... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 FIGURE 8- ...
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... PIC16F610/616/16HV610/616 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 C12IN0- 0 C12IN1- 1 MUX C12IN2- 2 C12IN3- 3 C1R C1IN+ 0 MUX C1V REF 1 Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Output shown for reference only. See I/O port pin block diagram for more detail. ...
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... See Section 8.11 “Comparator Voltage Reference” for more information on the internal voltage reference module. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.2.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by control ...
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... PIC16F610/616/16HV610/616 8.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figure 8-2 and Figure 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read ...
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... INTCON register is also set, the device will then execute the interrupt service routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their OFF states. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 61 ...
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... PIC16F610/616/16HV610/616 REGISTER 8-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 C1ON C1OUT C1OE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit ...
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... C2 connects to C12IN2 C2V - pin of C2 connects to C12IN3- IN Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 U-0 C2POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > C2V - ...
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... PIC16F610/616/16HV610/616 8.7 Comparator Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes analog input, therefore, must be between V If the input voltage deviates from this range by more than 0 ...
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... Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit Output is synchronous to falling edge of Timer1 clock Output is asynchronous © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register ...
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... PIC16F610/616/16HV610/616 8.9 Comparator Hysteresis Each comparator has built-in hysteresis that is user enabled by setting the C1HYS or C2HYS bits of the CM2CON1 register. The hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. FIGURE 8-7: COMPARATOR HYSTERESIS ...
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... TRISC TRISC5 VRCON C1VREN C2VREN VRR Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 (1) (1) ANS4 ANS3 ANS2 ANS1 C1POL C1SP ...
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... PIC16F610/616/16HV610/616 8.10 Comparator SR Latch The SR latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs. The SR latch may also be set or reset, independent of comparator output, by control bits in the SRCON0 control register ...
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... F /16 OSC /32 OSC /64 OSC /128 OSC bit 5-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 R/S-0 R/S-0 C2REN PULSS PULSR S = Bit is set only - U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) U-0 U-0 U-0 — ...
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... PIC16F610/616/16HV610/616 8.11 Comparator Voltage Reference The comparator voltage reference module provides an internally generated voltage reference comparators. The following features are available: • Independent from Comparator operation • Two 16-level voltage ranges • Output clamped • Ratiometric with V DD • Fixed Reference (0.6V) The VRCON register (Register 8-6) controls the voltage reference module shown in Figure 8-9 ...
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... ADC Module C1VREN C2VREN To ADC Module Fixed Ref To Comparators and ADC Module © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 8.11.7 VOLTAGE REFERENCE SELECTION , with DD Multiplexers on the output of the voltage reference module enable selection of either the CV voltage reference for use by the comparators. ...
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... PIC16F610/616/16HV610/616 REGISTER 8-6: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit circuit powered on and routed to C1V REF 0 = 0.6 Volt constant reference routed to C1V ...
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... RA0/AN0 RA1/AN1/V REF RA2/AN2 RA4/AN3 RC0/AN4 RC1/AN5 RC2/AN6 RC3/AN7 CV REF 0.6V Reference 1.2V Reference CHS <3:0> © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Note: The ADRESL and ADRESH registers are read-only. (ADC) allows V DD VCFG = 0 V VCFG = 1 REF ADC GO/DONE ADFM ADON ...
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... PIC16F610/616/16HV610/616 9.1 ADC Configuration When configuring and using the ADC, the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... Please see Section 9.1.5 “Interrupts” for more information. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT (ADFM = 0) MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 CYCLES ...
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... PIC16F610/616/16HV610/616 9.2 ADC Operation 9.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the analog-to-digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “ ...
Page 77
... BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 77 ...
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... PIC16F610/616/16HV610/616 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ADFM: A/D Conversion Result Format Select bit ...
Page 79
... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 0 ...
Page 80
... PIC16F610/616/16HV610/616 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY) R-x R-x R-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result ...
Page 81
... Note 1: The reference voltage (V REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ) SS ) impedance SS = 50°C and external impedance of 10k ...
Page 82
... PIC16F610/616/16HV610/616 FIGURE 9-4: ANALOG INPUT MODEL ANx Rs C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h ...
Page 83
... TRISC5 Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Note 1: PIC16F616/16HV616 only. 2: Read-only Register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — — ...
Page 84
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 84 © 2009 Microchip Technology Inc. ...
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... PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. ...
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... PIC16F610/616/16HV610/616 10.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • ...
Page 87
... TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 INTE ...
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... PIC16F610/616/16HV610/616 10.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • Toggle the CCP1 output • Set the CCP1 output • Clear the CCP1 output • ...
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... TRISC — — TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 DC1B0 CCP1M3 CCP1M2 CCP1M1 INTE ...
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... PIC16F610/616/16HV610/616 10.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCP1 pin ...
Page 91
... Timer Prescale (1, 4, 16) 16 PR2 Value 0x65 Maximum Resolution (bits) 8 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 EQUATION 10-2: Pulse Width EQUATION 10-3: • OSC Duty Cycle Ratio The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation ...
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... PIC16F610/616/16HV610/616 10.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. ...
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... Full-Bridge, Forward 01 Full-Bridge, Reverse 11 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. ...
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... PIC16F610/616/16HV610/616 FIGURE 10-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) Signal P1M<1:0> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active P1B Inactive (Full-Bridge, 01 Forward) P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, P1B Modulated 11 Reverse) P1C Active P1D Inactive Relationships: • ...
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... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 10.4.6 “Programmable Dead-Band Delay mode”). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Pulse 0 Width Period (1) (1) Delay Delay PR2+1 ...
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... PIC16F610/616/16HV610/616 10.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 10-8). This mode can be used for half-bridge applications, as ...
Page 97
... EXAMPLE OF FULL-BRIDGE APPLICATION P1A P1B P1C P1D © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs. V+ ...
Page 98
... PIC16F610/616/16HV610/616 FIGURE 10-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. DS41288F-page 98 Period (1) Period (1) © ...
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... When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer2 counts. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required ...
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... PIC16F610/616/16HV610/616 FIGURE 10-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE P1A P1B P1C P1D External Switch C External Switch D Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. ...
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... Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 DS41288F-page 101 ...
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... PIC16F610/616/16HV610/616 10.4.4 ENHANCED PWM AUTO- SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application ...
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... FIGURE 10-15: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1) Shutdown Event ECCPASE bit PWM Activity Start of PWM Period © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown ...
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... PIC16F610/616/16HV610/616 10.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off ...
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... Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare and PWM. Note 1: PIC16F616/16HV616 only. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 106 © 2009 Microchip Technology Inc. ...
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... See Figure 11-1 for voltage regulator schematic. FIGURE 11-1: VOLTAGE REGULATOR V UNREG R I SER SUPPLY I SHUNT C Feedback BYPASS © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 An external current limiting resistor, R between the unregulated supply, V pin, drops the difference in voltage between V and SER defined by Equation 11- EQUATION 11-1: supply current R MAX ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 108 © 2009 Microchip Technology Inc. ...
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... SPECIAL FEATURES OF THE CPU The PIC16F610/616/16HV610/616 has a host of features intended to maximize system reliability, minimize cost through elimination components, provide power-saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...
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... PIC16F610/616/16HV610/616 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — bit 15 (2) IOSCFS CP MCLRE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘1’ bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits 11 = BOR enabled ...
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... On-Chip 11-bit Ripple Counter RC OSC Note 1: Refer to the Configuration Word register (Register 12-1). © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation ...
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... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC16F610/616/16HV610/616 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
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... V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 On any Reset (Power-on, Brown-out Reset, Watchdog timer, etc.), the chip will remain in Reset until V above V (see Figure 12-3). If enabled, the Power- BOR up Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms ...
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... Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC16F610/616/ 16HV610/616 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers ...
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... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 T PWRT T PWRT T PWRT T OST T OST ) DD T OST DS41288F-page 115 ...
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... PIC16F610/616/16HV610/616 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS Power-on Register Address Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx PORTA 05h --x0 x000 PORTC 07h --xx xx00 PCLATH ...
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... Legend unchanged unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 MCLR Reset WDT Reset (Continued) (1) Brown-out Reset ...
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... PIC16F610/616/16HV610/616 12.4 Interrupts The PIC16F610/616/16HV610/616 sources of interrupt: • External Interrupt RA2/INT • Timer0 Overflow Interrupt • PORTA Change Interrupts • 2 Comparator Interrupts • A/D Interrupt (PIC16F616/16HV616 only) • Timer1 Overflow Interrupt • Timer2 Match Interrupt (PIC16F616/16HV616 only) • Enhanced CCP Interrupt (PIC16F616/16HV616 ...
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... ADIE (2) CCP1IF (2) CCP1IE © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 12.4.3 PORTA INTERRUPT-ON-CHANGE An input change on PORTA sets the RAIF bit of the INTCON register. The interrupt can be enabled/ disabled by setting/clearing the RAIE bit of the INTCON register. Plus, individual pins can be configured through the IOCA register. ...
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... PIC16F610/616/16HV610/616 FIGURE 12-8: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) INTF flag (5) (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC – 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3 the same whether Inst (PC single cycle or a 2-cycle instruction. ...
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... Execute the ISR code • Restore the Status (and Bank Select Bit register) • Restore the W register Note: The PIC16F610/616/16HV610/616 does not require saving the PCLATH. However, if computed GOTO’s are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR ...
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... PIC16F610/616/16HV610/616 12.6 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which requires no external components. This RC oscillator is separate from the external RC oscillator of the CLKIN pin and INTOSC. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped (for example, by execution of a SLEEP instruction) ...
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... T0CS (1) CONFIG IOSCFS CP MCLRE Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Bit 4 Bit 3 Bit 2 Bit 1 T0SE PSA PS2 PS1 PWRTE WDTE FOSC2 ...
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... PIC16F610/616/16HV610/616 12.7 Power-Down Mode (Sleep) The Power-Down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance) ...
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... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 OST (2) T (3) Interrupt Latency Processor in ...
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... PIC16F610/616/16HV610/616 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC16F610/616/16HV610/ 616 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. ...
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... DD CS0 2 27 CS1 3 26 CS2 4 25 RA5 5 24 RA4 6 23 RA3 7 22 RC5 8 21 RC4 9 20 RC3 ICDCLK 12 17 ICDMCLR 13 16 ICDDATA 14 15 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 GND RA0 RA1 SHUNTEN RA2 RC0 RC1 RC2 ICD DS41288F-page 127 ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 128 © 2009 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC16F610/616/16HV610/616 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
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... PIC16F610/616/16HV610/616 TABLE 13-2: PIC16F610/616/16HV610/616 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...
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... Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 BCF Syntax: k Operands: Operation: Status Affected: Description: ...
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... PIC16F610/616/16HV610/616 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...
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... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 INCFSZ Syntax: Operands: Operation: Status Affected: Description: ...
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... PIC16F610/616/16HV610/616 MOVF Move f Syntax: [ label ] MOVF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (f) → (dest) Operation: Status Affected: Z Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’ destination is W register the destination is file register ‘f’ ...
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... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 RETLW Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example: TABLE DONE RETURN Syntax: Operands: Operation: ...
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... PIC16F610/616/16HV610/616 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘ ...
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... Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF f,d 0 ≤ ...
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... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 138 © 2009 Microchip Technology Inc. ...
Page 139
... Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 14.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
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... PIC16F610/616/16HV610/616 14.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
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... Microchip Technology Inc. PIC16F610/616/16HV610/616 14.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
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... PIC16F610/616/16HV610/616 14.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ........................................................................... -0. )...............................................................................................................± ).........................................................................................................± ...
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... PIC16F610/616/16HV610/616 FIGURE 15-1: PIC16F610/616 VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: PIC16HV610/616 VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 5.0 4 ...
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... FIGURE 15-3: PIC16F610/616 FREQUENCY TOLERANCE GRAPH, ≤ ≤ -40°C T +125°C A 125 -40 2.0 2.5 FIGURE 15-4: PIC16HV610/616 FREQUENCY TOLERANCE GRAPH, ≤ ≤ -40°C T +125°C A 125 -40 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ± 5% ± 2% ± 1% 3.0 3.5 4.0 4.5 ...
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... PIC16F610/616/16HV610/616 15.1 DC Characteristics: PIC16F610/616/16HV610/616-I (Industrial) PIC16F610/616/16HV610/616-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 PIC16F610/616 D001 PIC16HV610/616 D001B PIC16F610/616 D001B PIC16HV610/616 D001C PIC16F610/616 D001C PIC16HV610/616 D001D PIC16F610/616 D001D PIC16HV610/616 D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR ...
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... DC Characteristics: PIC16F610/616-I (Industrial) PIC16F610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( PIC16F610/616 D011* D012 D013* D014 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... PIC16F610/616/16HV610/616 15.3 DC Characteristics: PIC16HV610/616-I (Industrial) PIC16HV610/616-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( PIC16HV610/616 D011* D012 D013* D014 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 149
... DC Characteristics: PIC16F610/616- I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (2) Current PIC16F610/616 D021 D022 D023 D024 D025 D026* D027 D028 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 150
... DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2) Current ( PIC16F610/616 D021E D022E D023E D024E D025E D026E* D027E D028E * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 151
... The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied Shunt regulator is always enabled and always draws operating current. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 - I (Industrial) -40°C ≤ T ≤ +85°C for industrial A Min Typ† ...
Page 152
... PIC16F610/616/16HV610/616 15.7 PIC16HV610/616 DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2, 3) Current ( PIC16HV610/616 D021E D022E D023E D024E D025E D026E* D027E D028E * These parameters are characterized but not tested. † Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 153
... This specification applies to all weak pull-up pins, including the weak pull-up on RA3/MCLR. When RA3/MCLR is configured as MCLR reset pin, the weak pull-up is always enabled. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 PIC16F610/616/16HV610/616 - I (Industrial) PIC16F610/616/16HV610/616 - E (Extended) Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ† ...
Page 154
... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended to use an external clock in RC mode. DS41288F-page 154 PIC16F610/616/16HV610/616 - I (Industrial) PIC16F610/616/16HV610/616 - E (Extended) Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ† ...
Page 155
... These parameters are characterized but not tested. Note current to run the chip alone without driving any load on the output pins Ambient Temperature. A © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Typ Units 70* C/W 14-pin PDIP package 85.0* C/W 14-pin SOIC package 100* C/W ...
Page 156
... PIC16F610/616/16HV610/616 15.11 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O Port mc MCLR Uppercase letters and their meanings Fall ...
Page 157
... AC Characteristics: PIC16F610/616/16HV610/616 (Industrial, Extended) FIGURE 15-6: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ≤ +125°C Operating temperature A Param Sym Characteristic No. OS01 F External CLKIN Frequency ...
Page 158
... PIC16F610/616/16HV610/616 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ≤ +125°C Operating Temperature A Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS07 INT Internal Calibrated OSC (2) INTOSC Frequency (4MHz) OS08 INT Internal Calibrated OSC ...
Page 159
... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output Includes OSC2 in CLKOUT mode. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Fetch Read Q1 Q2 OS11 OS20 ...
Page 160
... PIC16F610/616/16HV610/616 FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 15-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...
Page 161
... By design. 3: Period of the slower clock ensure these voltage tolerances, V possible. 0.1 μF and 0.01 μF values in parallel are recommended. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ≤ +125°C Min Typ† Max Units 2 — — 5 — ...
Page 162
... PIC16F610/616/16HV610/616 FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ≤ +125°C Operating Temperature A Param Sym Characteristic No. 40 T0CKI High Pulse Width ...
Page 163
... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 CC01 CC02 CC03 ≤ +125°C ...
Page 164
... PIC16F610/616/16HV610/616 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating Temperature A Param Sym Characteristics No. CM01 V Input Offset Voltage OS CM02 V Input Common Mode Voltage CM CM03* C Common Mode Rejection Ratio MRR (1) CM04* T Response Time RT CM05 Comparator Mode Change to Output Valid ...
Page 165
... When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module for PIC16HV616. REF © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Standard Operating Conditions (unless otherwise stated) Operating temperature Min Typ Max 4. ...
Page 166
... PIC16F610/616/16HV610/616 TABLE 15-12: PIC16F616/16HV616 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature A Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T ...
Page 167
... T OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 ( AD131 AD130 OLD_DATA Sampling Stopped is added before the A/D clock starts. This allows the ...
Page 168
... PIC16F610/616/16HV610/616 15.13 High Temperature Operation This section outlines the specifications for the PIC16F616 device operating in a temperature range (4) between -40°C and 150°C. The specifications (4) between -40°C and 150°C are identical to those shown in DS41302 and DS80329. Note 1: Writes are not allowed for Flash Program Memory above 125° ...
Page 169
... Supply Current ( D011 μA D012 μA mA D013 μA D014 μA mA D016 μA μA D017 mA D018 μA D019 mA © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 SPECIFICATIONS FOR PIC16F616 – H (High DD Min Typ Max V DD — 2.0 — 3.0 — 5.0 — 135 316 2.0 — ...
Page 170
... PIC16F610/616/16HV610/616 TABLE 15-15: DC CHARACTERISTICS FOR I Param Device Units No. Characteristics D020E μA Power Down I PD D021E μA D022E μA D023E μA μA D024E μA D025E μA D026E μA D027E μA TABLE 15-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic No ...
Page 171
... TABLE 15-19: COMPARATOR SPECIFICATIONS FOR PIC16F616 – H (High Temp.) Param Sym Characteristic No. CM01 V Input Offset Voltage OS © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Frequency Units Min Typ Tolerance ±10% MHz 7.2 and V must be capacitively decoupled as close to ...
Page 172
... PIC16F610/616/16HV610/616 NOTES: DS41288F-page 172 © 2009 Microchip Technology Inc. ...
Page 173
... FIGURE 16-1: PIC16F610/616 I 60 Typical: Statistical Mean @25°C 50 Maximum: Mean (Worst-Case Temp) + 3σ ...
Page 174
... Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 600 400 200 FIGURE 16-5: PIC16F610/616 I 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 600 400 200 0 1 DS41288F-page 174 EC (4 MHz) vs ...
Page 175
... FIGURE 16-6: PIC16F610/616 I 900 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp σ 700 (-40°C to 125°C) 600 500 400 300 200 100 FIGURE 16-7: PIC16F610/616 I 1800 Typical: Statistical Mean @25°C 1600 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) ...
Page 176
... Typical: Statistical Mean @25°C 700 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 600 500 400 300 200 100 FIGURE 16-9: PIC16F610/616 I Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) DS41288F-page 176 EXTRC (4 MHz (20 MHz) vs ...
Page 177
... FIGURE 16-10: PIC16F610/616 I 9 Typical: Statistical Mean @25°C 8 Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 7 (-40°C to 125° FIGURE 16-11: PIC16F610/616 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 BASE vs (V) DD COMPARATOR (SINGLE ON) vs Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ ...
Page 178
... PIC16F610/616/16HV610/616 FIGURE 16-12: PIC16F610/616 I 160 150 140 130 120 110 100 FIGURE 16-13: PIC16F610/616 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ 16 (-40°C to 85°C) 14 Extended: Mean (Worst-Case Temp) + 3σ (-40°C to 125° DS41288F-page 178 COMPARATOR (BOTH ON) vs Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ ...
Page 179
... FIGURE 16-14: PIC16F610/616 I 20 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) Extended: Mean (Worst-Case Temp (-40°C to 125° FIGURE 16-15: PIC16F610/616 I 140 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp (-40°C to 85°C) 120 Extended: Mean (Worst-Case Temp (-40° ...
Page 180
... Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp 100 (-40°C to 85°C) Extended: Mean (Worst-Case Temp (-40°C to 125° FIGURE 16-17: PIC16F610/616 I 25 Typical: Statistical Mean @25°C Industrial: Mean (Worst-Case Temp) + 3σ (-40°C to 85°C) Extended: Mean (Worst-Case Temp) + 3σ 20 (-40°C to 125° ...
Page 181
... FIGURE 16-19: PIC16HV610/616 I 450 Typical: Statistical Mean @25°C 400 Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) 300 250 200 150 100 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 A (32 kHz) vs (V) DD Extended Industrial Typical 5 6 Maximum Typical 5 4 ...
Page 182
... PIC16F610/616/16HV610/616 FIGURE 16-20: PIC16HV610/616 I 1000 Typical: Statistical Mean @25°C 900 Maximum: Mean (Worst-Case Temp) + 3σ 800 (-40°C to 125°C) 700 600 500 400 300 200 100 1 FIGURE 16-21: PIC16HV610/616 I 1400 Typical: Statistical Mean @25°C 1200 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) ...
Page 183
... FIGURE 16-25: PIC16HV610/616 I 2000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 1500 (-40°C to 125°C) 1000 500 0 1 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 XT (4 MHz) vs (V) DD INTOSC (4 MHz) vs (V) DD INTOSC (8 MHz) vs ...
Page 184
... PIC16F610/616/16HV610/616 FIGURE 16-26: PIC16HV610/616 I 1200 Typical: Statistical Mean @25°C 1000 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 800 600 400 200 0 1 FIGURE 16-27: PIC16HV610/616 I 400 Typical: Statistical Mean @25°C 350 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 300 ...
Page 185
... FIGURE 16-31: PIC16HV610/616 I 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 350 (-40°C to 125°C) 300 250 200 150 100 2 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 COMPARATOR (BOTH ON) vs (V) DD WDT vs (V) DD BOR vs (V) ...
Page 186
... PIC16F610/616/16HV610/616 FIGURE 16-32: PIC16HV610/616 I 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 400 (-40°C to 125°C) 300 200 100 0 1 FIGURE 16-33: PIC16HV610/616 I 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ 400 (-40°C to 125°C) 300 200 ...
Page 187
... OVER TEMPERATURE ( 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 5.0 5.5 6.0 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 A 3.0V) DD 6.5 7.0 7.5 8.0 I (mA) OL Maximum Typical ...
Page 188
... PIC16F610/616/16HV610/616 FIGURE 16-37: V vs. I OVER TEMPERATURE ( 0.45 Typical: Statistical Mean @25°C 0.40 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 FIGURE 16-38: V vs. I OVER TEMPERATURE ( 3.5 3.0 2.5 2.0 1.5 Typical: Statistical Mean @25° ...
Page 189
... TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 1.3 1.1 0.9 0.7 0.5 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 = 5.0V) DD -1.5 -2.0 -2.5 -3.0 -3.5 I (mA) OH vs. V OVER TEMPERATURE IN DD Max. -40° ...
Page 190
... PIC16F610/616/16HV610/616 FIGURE 16-41: SCHMITT TRIGGER INPUT THRESHOLD V 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 2.0 2.5 FIGURE 16-42: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40°C ...
Page 191
... Microchip Technology Inc. PIC16F610/616/16HV610/616 OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3σ ...
Page 192
... PIC16F610/616/16HV610/616 FIGURE 16-45: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 16-46: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41288F-page 192 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25°C) DD 5.0 5.5 (85°C) DD 4.5 5.0 5.5 © 2009 Microchip Technology Inc. ...
Page 193
... FIGURE 16-47: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 16-48: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125°C) DD 5.0 5.5 (-40°C) DD 5.0 5.5 DS41288F-page 193 ...
Page 194
... PIC16F610/616/16HV610/616 FIGURE 16-49: 0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 0.61 0.6 0.59 0.58 0.57 0.56 -60 -40 -20 FIGURE 16-50: 1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL) 1.26 1.25 1.24 1.23 1.22 1.21 1.2 -60 -40 -20 FIGURE 16-51: SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL) 5.16 5.14 5.12 5 ...
Page 195
... COMPARATOR RESPONSE TIME (RISING EDGE) 1000 900 800 700 Vcm = (V - 1.5V)/2 Note: 600 DD V+ input = Vcm V- input = Transition from Vcm + 100mV to Vcm - 20mV 500 400 300 200 100 0 2.0 © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Temp (C) 2.5 4 100 120 140 Max. 125° ...
Page 196
... PIC16F610/616/16HV610/616 FIGURE 16-54: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 700 600 Note 1.5V)/ input = V CM 500 V- input = Transition from V 400 300 200 100 0 2.0 FIGURE 16-55: WDT TIME-OUT PERIOD vs 1.5 2 DS41288F-page 196 - 100 2.5 4.0 V (V) DD OVER TEMPERATURE DD 2 ...
Page 197
... Microchip part number, year code, week code, and traceability ® code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2009 Microchip Technology Inc. PIC16F610/616/16HV610/616 Example PIC16F616 e -I/P 0610017 ...
Page 198
... PIC16F610/616/16HV610/616 17.2 Package Details The following sections give the technical details of the packages. DS41288F-page 198 © 2009 Microchip Technology Inc. ...
Page 199
... Microchip Technology Inc. PIC16F610/616/16HV610/616 φ α β DS41288F-page 199 ...
Page 200
... PIC16F610/616/16HV610/616 DS41288F-page 200 © 2009 Microchip Technology Inc. ...