PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet
PIC18F4580-I/ML
Specifications of PIC18F4580-I/ML
Related parts for PIC18F4580-I/ML
PIC18F4580-I/ML Summary of contents
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... PIC18F2480/2580/4480/4580 Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D © 2009 Microchip Technology Inc. Data Sheet 28/40/44-Pin and nanoWatt Technology DS39637D ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F2480 16K 8192 PIC18F2580 32K 16384 PIC18F4480 16K 8192 PIC18F4580 32K 16384 © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Three External Interrupts • One Capture/Compare/PWM (CCP) module • Enhanced Capture/Compare/PWM (ECCP) module (40/44-pin devices only): ...
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... RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 RC7/RX/DT RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/FLT0/AN10 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2IN- RD2/PSP2/C2IN+ © 2009 Microchip Technology Inc. ...
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... RB1/INT1/AN8 RB2/INT2/CANTX Note 1: For the QFN package recommended that the bottom pad be connected to V © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 PIC18F4480 28 6 PIC18F4580 PIC18F4480 PIC18F4580 RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI . SS DS39637D-page 5 ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 473 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 473 The Microchip Web Site ..................................................................................................................................................................... 487 Customer Change Notification Service .............................................................................................................................................. 487 Customer Support .............................................................................................................................................................................. 487 Reader Response .............................................................................................................................................................................. 488 PIC18F2480/2580/4480/4580 Product Identification System ............................................................................................................ 489 DS39637D-page 6 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 DS39637D-page 7 ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 8 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F2480 • PIC18F2580 • PIC18F4480 • PIC18F4580 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, ...
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... Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2580), accommodate an operating V range of 4.2V to 5.5V. DD Low-voltage parts, designated by “LF” (such as PIC18LF2580), function over an extended V of 2.0V to 5.5V. © 2009 Microchip Technology Inc. for for have one only on range ...
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... WDT Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled Enabled 28-pin SPDIP 28-pin SPDIP 28-pin SOIC 28-pin SOIC 28-pin QFN 28-pin QFN PIC18F4480 PIC18F4580 DC – 40 MHz DC – 40 MHz 16384 32768 8192 16384 768 1536 256 256 20 20 Ports Ports ...
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... MSSP EUSART 10-Bit PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/INT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (1) MCLR/V /RE3 PP ECAN © 2009 Microchip Technology Inc. ...
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... RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 3.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Data Bus<8> Data Latch ...
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... Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output C™/SMBus input buffer © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog Input 0. ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output C™/SMBus input buffer © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — Timer1 oscillator output Timer1/Timer3 external clock input. ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output C™/SMBus input buffer © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type TQFP PORTA is a bidirectional I/O port. 19 I/O TTL Digital I/O. I Analog Analog Input 0 ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output C™/SMBus input buffer © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type TQFP PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output. ...
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... ECCP1 PWM Output B. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O TTL ECCP1 PWM Output C. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O TTL ECCP1 PWM Output D. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... NC — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output C™/SMBus input buffer © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Pin Buffer Type Type TQFP PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. I TTL Read control for Parallel Slave Port (see also WR and CS pins) ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 24 © 2009 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 FIGURE 2- MCLR ( ...
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... V DD Note: Not all devices incorporate software BOR control. See Section 5.0 “Reset” for device-specific information. may result in a spontaneous DD does not approach the set point. DD and circuit as the microcontroller © 2009 Microchip Technology Inc. ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 © 2009 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel resonant crystal. Note: Use of a series resonant crystal may give a frequency out of manufacturer’s specifications. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 FIGURE 3-1: (1) C1 (1) C2 Note 1: See Table 3-1 and Table 3-2 for initial values of C1 and C2. ...
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... Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2009 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 3.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Section 3.6.5.1 “Compensating with the EUSART”, Section 3.6.5.2 “Compensating with the Timers” and Section 3.6.5.3 “Compensating with the CCP Module in Capture Mode”, but other techniques may be used. or temperature changes, which can compensation techniques are © 2009 Microchip Technology Inc. ...
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... Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 ...
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... MHz 101 1 MHz 100 500 kHz 011 250 kHz FOSC<3:0> 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> © 2009 Microchip Technology Inc. Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for Other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. DS39637D-page 36 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 5-2 in Section 5.0 “Reset”, for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Timer1 oscillator may be operating to support a Real-Time Clock (RTC). Other features may be operat- ing that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others) ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 38 © 2009 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... SEC_RUN mode will not occur. If the Timer1 oscillator is enabled but not yet running, device clocks will be delayed until the oscillator has started. In such situa- tions, initial oscillator operation is far from stable and unpredictable operation may result. EXECUTING BACK-TO-BACK SLEEP INSTRUCTIONS © 2009 Microchip Technology Inc. ...
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... RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition (1) (1) OST T PLL 1 2 n-1 n Clock Transition PC OSTS Bit Set © 2009 Microchip Technology Inc. ...
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... Wake Event Note1 1024 (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 4.4 Idle Modes in the The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON< ...
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... IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status bit (OSCCON) OSTS (2) — IOFS (4) (4) OSTS + t rc (2) — (5) IOFS (5) (4) OSTS + t rc (2) — IOFS (4) (4) OSTS + t rc (2) — (5) IOFS © 2009 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 5-2 for time-out situations. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39637D-page 48 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 FIGURE 5-2: V ...
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... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. and operates as previously © 2009 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 5.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39637D-page PWRT T OST T PWRT T OST T PWRT T OST © 2009 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 , V RISE > PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register (1) SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( ( STKPTR Register POR BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... The PIC18F2480 and PIC18F4480 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The PIC18F2580 and PIC18F4580 each have 32 Kbytes of Flash memory and can store up to 16,384 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. nn ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 6.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 6.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... FFh = 1100 00h Bank 12 FFh = 1101 00h Bank 13 FFh 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR ...
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... This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 peripheral functions. The reset and interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section ...
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... F0Dh RXF3SIDL TXB2D6 F0Ch RXF3SIDH TXB2D5 F0Bh RXF2EIDL TXB2D4 F0Ah RXF2EIDH TXB2D3 F09h RXF2SIDL TXB2D2 F08h RXF2SIDH TXB2D1 F07h RXF1EIDL TXB2D0 F06h RXF1EIDH TXB2DLC F05h RXF1SIDL F04h RXF1SIDH F03h RXF0EIDL F02h RXF0EIDH F01h RXF0SIDL F00h RXF0SIDH © 2009 Microchip Technology Inc. ...
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... Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Name Address EDFh — ...
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... E0Bh — — E0Ah — — E09h — — E08h — — E07h — — E06h — — E05h — — E04h — — E03h — — E02h — — E01h — — E00h — © 2009 Microchip Technology Inc. ...
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... Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Name Address — DBFh — ...
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... D61h RXF6SIDL D60h RXF6SIDH Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. DS39637D-page 82 © 2009 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 4 Bit 3 Bit 2 — ...
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... PDC1 PDC0 57, 187 0000 0000 (3) (3) PSSBD1 PSSBD0 57, 187 0000 0000 CVR1 CVR0 57, 269 0000 0000 CM1 CM0 57, 263 0000 0000 57, 165 xxxx xxxx 57, 165 xxxx xxxx TMR3CS TMR3ON 0000 0000 57, 165 © 2009 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 4 Bit 3 Bit 2 ...
Page 86
... RXB0D11 RXB0D10 59, 298 xxxx xxxx RXB0D01 RXB0D00 59, 298 xxxx xxxx DLC1 DLC0 59, 298 -xxx xxxx EID1 EID0 59, 297 xxxx xxxx EID9 EID8 xxxx xxxx 59, 297 EID17 EID16 59, 297 xxxx x-xx SID4 SID3 59, 296 xxxx xxxx © 2009 Microchip Technology Inc. ...
Page 87
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 4 Bit 3 Bit 2 (7) — ...
Page 88
... EID1 EID0 61, 309 xxxx xxxx EID9 EID8 61, 309 xxxx xxxx EID17 EID16 61, 308 xxx- x-xx SID4 SID3 61, 308 xxxx xxxx EID1 EID0 xxxx xxxx 61, 309 EID9 EID8 61, 309 xxxx xxxx EID17 EID16 62, 308 xxx- x-xx © 2009 Microchip Technology Inc. ...
Page 89
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 4 Bit 3 Bit 2 ...
Page 90
... EID17 EID16 63, 303 xxx- x-xx SID4 SID3 63, 302 xxxx xxxx FILHIT1 FILHIT0 63, 301 0000 0000 TXPRI1 TXPRI0 63, 301 0000 0000 B2D71 B2D70 xxxx xxxx 63, 305 B2D61 B2D60 63, 305 xxxx xxxx B2D51 B2D50 63, 305 xxxx xxxx © 2009 Microchip Technology Inc. ...
Page 91
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 4 Bit 3 Bit 2 ...
Page 92
... F4BP_1 F4BP_0 65, 312 0001 0001 F2BP_1 F2BP_0 65, 312 0001 0001 F0BP_1 F0BP_0 65, 312 0000 0000 FLC1 FLC0 65, 312 ---0 0000 RXF9EN RXF8EN 65, 311 0000 0000 RXF1EN RXF0EN 65, 311 0000 0000 EID1 EID0 65, 309 xxxx xxxx © 2009 Microchip Technology Inc. ...
Page 93
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 4 Bit 3 Bit 2 ...
Page 94
... Table 26-2 and Table 26-3. Note: The C and DC bits operate as the borrow and digit borrow bits respectively in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 95
... Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 “General © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Purpose Register File” location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘ ...
Page 96
... RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 Bank 14 F00h Bank 15 FFFh Data Memory © 2009 Microchip Technology Inc. ...
Page 97
... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
Page 98
... Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 26.2.1 “Extended Instruction Syntax”. © 2009 Microchip Technology Inc. ...
Page 99
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 000h 060h Bank 0 080h 100h Bank 1 ...
Page 100
... BSR remains unchanged. Direct Addressing using the BSR to select the data memory bank operates in the same manner as previously described. Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2009 Microchip Technology Inc. ...
Page 101
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 102
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF Interrupt Flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
Page 103
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-x R/W-0 ...
Page 104
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TBLPTR<21:6> TABLE READ – TBLPTR<21:0> TBLPTRL 0 TABLE WRITE TBLPTR<5:0> © 2009 Microchip Technology Inc. ...
Page 105
... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 106
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
Page 107
... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The long write is necessary for programming the inter- nal Flash. Instruction execution is halted while in a long write cycle ...
Page 108
... TBLWT holding register. ; loop until buffers are full © 2009 Microchip Technology Inc. ...
Page 109
... These bits are available in PIC18F4X80 devices only. 2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 3: This bit is available only in Test mode and Serial Programming mode. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 110
... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 110 © 2009 Microchip Technology Inc. ...
Page 111
... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit, EEPGD, determines if the access will be to program or data EEPROM memory ...
Page 112
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39637D-page 112 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 113
... BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe- cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 114
... Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Disable writes ; Enable interrupts information (e.g., program © 2009 Microchip Technology Inc. ...
Page 115
... CMIF (1) PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 116
... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 116 © 2009 Microchip Technology Inc. ...
Page 117
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 ...
Page 118
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
Page 119
... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
Page 120
... INT1IP INT2IF INT2IE INT2IP IPE IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP GIEL/PEIE GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2009 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h ...
Page 121
... None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Note: Interrupt flag bits are set when an interrupt ...
Page 122
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39637D-page 122 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 ...
Page 124
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 125
... Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4X80 and reserved in PIC18F2X80 devices. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 126
... R/W-0 (1) ERRIF TXBnIF TXB1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (1) (1) (1) R/W-0 R/W-0 R/W-0 (1) TXB0IF RXB1IF RXB0IF R/W-0 R/W-0 R/W-0 (1) (1) TXB0IF RXBnIF FIFOWMIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2X80 devices; always maintain this bit clear. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 128
... This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 2: This bit is available in PIC18F4X80 devices only. DS39637D-page 128 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 (2) TMR3IE ECCP1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 (1) ERRIE ...
Page 130
... Low priority Note 1: This bit is reserved on PIC18F2X80 devices; always maintain this bit set. DS39637D-page 130 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... ECCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 2: This bit is available in PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ...
Page 132
... R/W-1 R/W-1 (1) ERRIP TXBnIP TXB1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (1) (1) R/W-1 R/W-1 R/W-1 (1) TXB0IP RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 (1) TXB0IP RXBnIP FIFOWMIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 133
... For details of bit operation, see Register 5-1. Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See Register 5-1 for additional information. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-1 R-1 R-1 RI ...
Page 134
... Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
Page 135
... PORT Note 1: I/O pins have diode protection to V © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 136
... Main oscillator input connection determined by FOSC<3:0> x Configuration bits. Enabling OSC1 overrides digital I/O. ANA Main clock input connection determined by FOSC<3:0> x Configuration bits. Enabling CLKI overrides digital I/O. DIG LATA<7> data output. 0 TTL PORTA<7> data input. 1 Description /4). OSC © 2009 Microchip Technology Inc. ...
Page 137
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: These registers are unimplemented on PIC18F2X80 devices. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 138
... RBIF cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. © 2009 Microchip Technology Inc. will end the ...
Page 139
... IN PGD OUT IN Legend: OUT = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Note 1: Available on 40/44-pin devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TRIS Buffer DIG LATB<0> data output. 0 TTL PORTB<0> data input. Weak pull-up available only in this mode. ...
Page 140
... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on Page: RB1 RB0 INT0IF RBIF 55 — RBIP 55 INT2IF INT1IF 55 PCFG1 PCFG0 56 © 2009 Microchip Technology Inc. ...
Page 141
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Note Power-on Reset, these pins are configured as digital inputs ...
Page 142
... EUSART synchronous data output – must have TRIS set to ‘1’ to enable EUSART to control the bidirectional communication. ST EUSART synchronous data input. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Description Reset Bit 1 Bit 0 Values on Page: RC1 RC0 © 2009 Microchip Technology Inc. ...
Page 143
... Section 21.0 “Comparator Module”. Note Power-on Reset, these pins are configured as analog inputs. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 11.6 “ ...
Page 144
... LATD<7> data output. ST PORTD<7> data input. DIG Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled). TTL Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled). DIG ECCP1 Enhanced PWM output, channel D. © 2009 Microchip Technology Inc. ...
Page 145
... TRISE IBF OBF (1) ECCP1CON EPWM1M1 EPWM1M0 EDC1B1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 ...
Page 146
... RE<2> as inputs 11.5.1 PORTE IN 28-PIN DEVICES For PIC18F2X80 devices, PORTE is only available when Master Clear functionality (MCLRE = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. © 2009 Microchip Technology Inc. is disabled ...
Page 147
... TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 U-0 R/W-1 PSPMODE — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 ...
Page 148
... RE3 RE2 — — — LATE Output Latch Register IBOV PSPMODE — TRISE2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 Description Reset Bit 1 Bit 0 Values on Page: RE1 RE0 58 58 TRISE1 TRISE0 58 PCFG1 PCFG0 56 CM1 CM0 57 © 2009 Microchip Technology Inc. ...
Page 149
... PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The timing for the control signals in Write and Read modes is shown in Figure 11-3 and Figure 11-4, respectively ...
Page 150
... RCIP TXIP SSPIP CCP1IP VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 Reset Bit 1 Bit 0 Values on Page: RD1 RD0 RE1 RE0 58 58 TRISE1 TRISE0 58 INT0IF RBIF 55 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 TMR2IP TMR1IP 58 PCFG1 PCFG0 56 CM1 CM0 57 © 2009 Microchip Technology Inc. ...
Page 151
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
Page 152
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 153
... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 12.3.1 SWITCHING PRESCALER ...
Page 154
... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 154 © 2009 Microchip Technology Inc. ...
Page 155
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 156
... Special Event Trigger) 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 157
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 158
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. a Special Event Trigger © 2009 Microchip Technology Inc. ...
Page 159
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 ; Preload TMR1 register pair ; for 1 second overflow ...
Page 160
... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 160 © 2009 Microchip Technology Inc. ...
Page 161
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options ...
Page 162
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 55 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
Page 163
... Enables Timer3 0 = Stops Timer3 Note 1: These bits and the ECCP module are available on PIC18F4X80 devices only. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. ...
Page 164
... Clear TMR3 TMR3L 8 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 165
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: These bits are available in PIC18F4X80 devices only. 2: These bits are available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h ...
Page 166
... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 166 © 2009 Microchip Technology Inc. ...
Page 167
... Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set) 11xx = PWM mode Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 The CCP1 module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register ...
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... PWM) at the same time. The interactions between the two modules are summarized in Figure 16-1 and Figure 16-2. Interaction © 2009 Microchip Technology Inc. ...
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... The user should keep the CCPxIE interrupt enable bit clear to avoid false inter- rupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 16.2.4 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP1M< ...
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... Set CCP1IF T3ECCP1 and Edge Detect T3ECCP1 4 Set ECCP1IF 4 4 T3CCP1 T3ECCP1 and Edge Detect T3ECCP1 T3CCP1 TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable ECCPR1H ECCPR1L TMR1 Enable TMR1H TMR1L © 2009 Microchip Technology Inc. ...
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... TMR3H TMR3L T3CCP1 Comparator ECCPR1H ECCPR1L © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 16.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
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... EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 55 POR BOR 56 TMR2IP TMR1IP 58 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 (2) TMR3IP ECCP1IP 58 (2) TMR3IF ECCP1IF 58 (2) TMR3IE ECCP1IE TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 © 2009 Microchip Technology Inc. ...
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... A PWM output (Figure 16-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 FIGURE 16-4: Duty Cycle TMR2 = PR2 16 ...
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... Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. ⎛ ⎞ F OSC log ⎝ ⎠ F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... Shaded cells are not used by PWM or Timer2. Note 1: These registers are unimplemented on PIC18F2X80 devices. 2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... PIC18F2480/2580/4480/4580 NOTES: DS39637D-page 176 © 2009 Microchip Technology Inc. ...
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... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 Enhanced features are discussed in detail in Section 17.4 “Enhanced PWM Mode”. Capture, ...
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... The latter is more generic, but will work for either single or multi-output PWM. and Timer RD4 RD5 All PIC18F4480/4580 Devices: CCP1 RD5/PSP5 P1A P1B P1A P1B and Section 16.3 “Compare for PWM Operation” or RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2009 Microchip Technology Inc. ...
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... ECCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 17.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
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... The general relationship of the outputs in all configurations is summarized in Figure 17-2. 9.77 kHz 39.06 kHz FFh FFh OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... Prescale Value) OSC • Duty Cycle = T * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 0 Duty Cycle Period (1) (1) Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
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... P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<7> data latches. The TRISD<4>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
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... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...
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... All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D signals Forward Period t1 ...
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... If the dead-band delay value is increased after the dead-band time has elapsed, that new value takes effect immediately. This happens even if the PWM pulse is high and can appear glitch. Dead-band values must be changed during the dead-band time or before ECCP is active on the © 2009 Microchip Technology Inc. ...
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... PSSBD<1:0>: Pins, B and D, Shutdown State Control bits 1x = Pins, B and D, tri-state 01 = Drive Pins, B and D, to ‘1’ Drive Pins, B and D, to ‘0’ Note 1: Reserved on PIC18F2X80 devices; maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 (1) (1) ...
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... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2009 Microchip Technology Inc. ...
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... PSSBD<1:0> bits. • Set the ECCPASE bit (ECCP1AS<7>). • Configure the comparators using the CMCON register. • Configure the comparator inputs as analog inputs. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 7. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 8. Configure and start TMR2: • ...
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... Bit 1 Bit 0 Values on Page: INT0IF RBIF 55 PD POR BOR 56 TMR2IP TMR1IP 58 TMR2IF TMR1IF 58 TMR2IE TMR1IE 58 (3) TMR3IP ECCP1IP 57 (3) TMR3IF ECCP1IF 58 (3) TMR3IE ECCP1IE TMR1CS TMR1ON 56 56 T2CKPS0 TMR3CS TMR3ON (2) (2) PSSBD0 57 (2) (2) (2) PDC1 PDC0 57 © 2009 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 18.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R bit Bit is unknown ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 R/W-0 R/W-0 R/W-0 (2) ...
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... Note: The SSPBUF register cannot be used with read-modify-write instructions such as BCF, BTFSC and COMF, etc. Note: To avoid lost data in Master mode, a read of the SSPBUF must be performed to clear the Buffer Full (BF) detect bit (SSPSTAT<0>) between each transmission. © 2009 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 18.3.4 TYPICAL CONNECTION Figure 18-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39637D-page 198 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
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... CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2X80 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2480/2580/4480/4580 18.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... SSPBUF and the SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. © 2009 Microchip Technology Inc. ...