PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 363

• Manufacturer Part Number: PIC18F4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 25-5:
© 2009 Microchip Technology Inc.
®
devices.
1FFFFFh
000FFFh
001FFFh
003FFFh
005FFFh
007FFFh
Address
000000h
0007FFh
000800h
001000h
002000h
004000h
006000h
008000h
Range
BBSIZ
Program Verification and
Code Protection
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
1 kW
3 kW
4 kW
4 kW
4 kW
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2480/2580/4480/4580
(PIC18F2580/4580)
0
32 Kbytes
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
MEMORY SIZE/DEVICE
2 kW
2 kW
4 kW
4 kW
4 kW
1
PIC18F2480/2580/4480/4580
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
1 kW
3 kW
4 kW
(PIC18F2480/4480)
0
16 Kbytes
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
Unimplemented
Boot Block
Read ‘0’s
Block 0
Block 1
2 kW
2 kW
4 kW
1
(Unimplemented Memory Space)
Block Code Protection
CPB, WRTB, EBRTB
CP0, WRT0, EBRT0
CP2, WRT2, EBRT2
CP3, WRT3, EBTR3
CP!, WRT1, EBRT1
Controlled by:
(Boot Block)
(Block 0)
(Block 1)
(Block 2)
(Block 3)
DS39637D-page 363