PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 262

• Manufacturer Part Number: PIC18F4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
20.7
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP1 module. This requires that the
ECCP1M<3:0> bits (ECCP1CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
TABLE 20-2:
DS39637D-page 262
INTCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
ADRESH A/D Result Register High Byte
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(4)
2:
3:
4:
5:
(4)
(4)
Use of the CCP1 Trigger
These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear.
These pins may be configured as port pins depending on the Oscillator mode selected.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers are not implemented on PIC18F2X80 devices.
These bits are available on PIC18F4X80 and reserved on PIC18F2X80 devices.
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
TRISA7
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register Low Byte
OSCFIP
OSCFIF
OSCFIE
PSPIP
PSPIF
PSPIE
RA7
ADFM
Bit 7
IBF
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(2)
(2)
TRISA6
RA6
CMIP
CMIF
CMIE
ADIP
ADIE
Bit 6
ADIF
OBF
—
—
—
—
—
(2)
(2)
PORTA Data Direction Register
VCFG1
ACQT2
CHS3
RCIP
RCIE
IBOV
RCIF
Bit 5
RA5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
CHS2
EEIP
EEIE
TXIP
TXIF
TXIE
EEIF
Bit 4
RA4
—
—
PCFG3
ACQT0
SSPIP
SSPIE
RE3
SSPIF
BCLIP
BCLIF
BCLIE
CHS1
RBIE
Bit 3
RA3
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3) coun-
ter.
—
—
ACQ
(3)
time selected before the “Special Event Trigger”
Read PORTE pins, Write LATE
PORTE Data Direction
TMR0IF
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIE
HLVDIF
PCFG2
ADCS2
LATE2
CHS0
Bit 2
RA2
GO/DONE
TMR2IP
TMR2IE
TMR3IP ECCP1IP
TMR3IE ECCP1IE
TMR2IF
TMR3IF
PCFG1
ADCS1
INT0IF
LATE1
Bit 1
RA1
© 2009 Microchip Technology Inc.
ECCP1IF
TMR1IP
TMR1IF
TMR1IE
PCFG0
ADCS0
LATE0
ADON
RBIF
Bit 0
RA0
(1)
(5)
(5)
(5)
on Page:
Values
Reset
55
58
58
58
57
58
58
56
56
56
56
57
58
58
58
58
58
58
58
58