ISL29002IROZ-T7 Intersil, ISL29002IROZ-T7 Datasheet - Page 5

• Manufacturer Part Number: ISL29002IROZ-T7
• Description: IC SENSOR LIGHT-DGTL I2C 8-ODFN
• Manufacturer: Intersil

Specifications of ISL29002IROZ-T7

• Wavelength: 550nm
• Output Type: I²C™
• Package / Case: 8-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL29002IROZ-T7; ISL29002IROZ-T7TR

Principles of Operation
Photodiodes and ADC
The ISL29002 contains two photodiodes. One of the
photodiodes is sensitive to visible and infrared light (Diode 1).
Another photodiode (Diode 2) is covered with metal and can be
used to cancel the effects of dark output code, the unwanted
number of counts in the absence of light. Diode 2 can also be
used to cancel the presence of IR. See IR rejection in the
applications section. The ISL29002 also contains an on-chip
integrating analog-to-digital converter (ADC) to convert
photodiode currents into digital data. The interface to the ADC
is implemented using the standard I
The ISL29002’s built-in ADC is a charge-balancing
integrating converter type. The integrating ADC converts the
photodiode current to frequency. The repetition rate is then
counted by a binary counter to output a digital code - number
of counts. The ISL29002 can be configured (in external
timing mode) to output a maximum 2
The ADC has two timing controls, internal timing and
external timing. With internal timing, the number of clock
cycles per integration time is fixed at 2
number of counts is limited to 2
timing, the user have the flexibility to vary the maximum
number of counts up to 2
In addition, the ADC has three operating modes (Please
consult Table 1 for a complete list of modes.) In the first
operating mode, the ADC only integrates Diode 1's current. In
the second operating mode, the ADC only integrates the other
diode, Diode 2’s current. Both operating mode 1 and mode 2
has a 16-bit unsigned-magnitude format. In the third operating
mode, the ADC integrates Diode 2's current first, then Diode 1's
current. In this mode, the output is a 16-bit 2’s complement
format. The total integration time is doubled, and the digital
output is the difference of the two photodiode currents (Diode
1’s current minus Diode 2’s current). Any of the three operating
modes can be used with either of the two timing controls, either
internally or externally controlled integration timing.
I
The ISL29002 contains a single 8-bit command register that
can be written via the I
defines the operation of the device, which does not change
until the command register is overwritten.
The ISL29002 contains four 8-bit data registers that can be
read via the I
the ADC's latest digital output, while the second two
registers contain the number of clock cycles in the previous
integration period.
The ISL29002’s I
and A2. These pins can be tied or driven either high or low.
They comprise the least-significant three bits of the I
address, while the four most-significant bits are hardwired as
2
C Interface
2
C interface. The first two data registers contain
2
C address is pin-selectable by pins A0, A1,
2
C interface. The command register
16
(65,536).
5
15
2
(32,7268). With external
C interface.
16
15
(65,536) counts.
(32,726), hence the
2
C
ISL29002
1000. The eight possible addresses are therefore 40H through
47H.
Figure 11B shows a sample one-byte read. (A typical
application will read two to four bytes, however.) The I
master always drives the SCL (clock) line, while either the
master or the slave can drive the SDA (data) line. Every I
transaction begins with the master asserting a start condition
(SDA falling while SCL remains high). The following byte is
driven by the master, and includes the slave address and
read/write bit. The receiving device is responsible for pulling
SDA low during the acknowledgement period.
Any writes to the ISL29002 overwrite the command register,
changing the device’s mode. Any reads from the ISL29002
return two or four bytes of sensor data and counter value,
depending upon the operating mode. Neither the command
register nor the data registers have internal addresses, and
none of the registers can be individually addressed.
Every I
condition (SDA rising while SCL remains high).
I
To WRITE, the master sends slave address 44(hex) plus the
write bit. Then master sends the ADC command to the
device which defines its operation. As soon as the ISL29002
receives the ADC command, it will execute and then store
the readings in the register after the analog-to-digital
conversion is complete. While the ISL29002 is executing the
command and also after the execution, the I
available for transactions other than the ISL29002. After
command execution, sensor data readings are stored in the
registers. Note that if a READ is received before the
execution is finished, the data retrieved is previous data
sensor reading. Typical integration/conversion time is 100ms
(for R
recommended that a READ is sent 120ms later because the
fosc variation is 20%.
The operation of the device does not change until the
command register is overwritten. Hence, when the master
sends a slave address 44(hex) and a write bit, the ISL29002
will repeat the same command from the previous WRITE
transaction.
To READ, master sends slave address 44(hex) plus the read
bit. Then ISL29002 will hold the SDA line to send data to
master. Note that the master need not send an address register
to access the data. As soon as the ISL29002 receives the read
bit. It will send 4 bytes. The 1st byte is the LSB of the sensor
reading. The 2nd byte is the MSB of the sensor reading. The
3rd byte is LSB of the counter reading. The 4th byte is the MSB
of the counter reading. If internal timing mode is selected, only
the 1st and 2nd data byte are necessary; the master can assert
a stop after the 2nd data byte is received.
For more information about the I
the Philips ® I
2
C Transaction Flow
EXT
2
C transaction ends with the master asserting a stop
= 100k and internal timing mode). It is
2
C specification documents.
2
C standard, please consult
2
C bus is
December 1, 2006
2
FN7465.2
C bus
2
C