VS6624Q0KP STMicroelectronics, VS6624Q0KP Datasheet - Page 94

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VS6624Q0KP

Manufacturer Part Number
VS6624Q0KP
Description
Display Modules & Development Tools CAMERA MODULE SINGLE CHIP 1.3MEGA
Manufacturer
STMicroelectronics
Datasheet

Specifications of VS6624Q0KP

Description/function
Camera Module
Interface Type
Two-Wire Serial
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Electrical characteristics
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Parallel data interface timing
VL6624/VS6624 contains a parallel data output port (D[7:0]) and associated qualification
signals (HSYNC, VSYNC, PCLK and FSO).
This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or
bit-serial output configurations. The port is disabled (high impedance) upon reset.
Figure 36. Parallel data output video timing
Table 51.
f
t
t
t
Symbol
PCLK
PCLKL
PCLKH
DV
PCLK
polarity = 0
HSYNC,
VSYNC
D[0:7]
PCLK frequency
PCLK low width
PCLK high width
PCLK to output valid
Parallel data interface timings
Description
t
DV
t
PCLKL
[1/2*(1/f
[1/2*(1/f
1/f
-5.15
Min.
PCLK
PCLK
PCLK
Valid
)] - 3.9
)] - 3.9
t
PCLKH
[1/2*(1/f
[1/2*(1/f
Max.
1.62
PCLK
PCLK
54
)] + 3.9
)] + 3.9
VL6624/VS6624
MHz
Unit
ns
ns
ns

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