EA-QSB-010 Embedded Artists, EA-QSB-010 Datasheet - Page 23

• Manufacturer Part Number: EA-QSB-010
• Description: MCU, MPU & DSP Development Tools LPC2148 USB QUICKSTART BRD
• Manufacturer: Embedded Artists

Specifications of EA-QSB-010

• Processor To Be Evaluated: LPC2148
• Data Bus Width: 16 bit, 32 bit
• Interface Type: RS-232, USB, I2C, SPI, UART
• Core: ARM7TDMI-S
• Dimensions: 59 mm x 39.5 mm
• Maximum Operating Temperature: + 85 C
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC2141_42_44_46_48_4
Product data sheet
6.19.4 Brownout detector
6.19.5 Code security
6.19.6 External interrupt inputs
6.19.7 Memory mapping control
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the V
this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal
can be enabled for interrupt; if not, software can monitor the signal by reading dedicated
register.
The second stage of low voltage detection asserts reset to inactivate the
LPC2141/42/44/46/48 when the voltage on the V
prevents alteration of the flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be
protected from observation. Once debugging is disabled, it can be enabled only by
performing a full chip erase using the ISP.
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake-up the processor from Power-down mode.
Additionally capture input pins can also be used as external interrupts without the option
to wake the device up from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
Rev. 04 — 17 November 2008
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ramp (in the case of power on), the type of crystal
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
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pins falls below 2.6 V. This reset
© NXP B.V. 2008. All rights reserved.
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pins. If
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