DK-PCIE-ECP2M-011 Lattice, DK-PCIE-ECP2M-011 Datasheet - Page 16

• Manufacturer Part Number: DK-PCIE-ECP2M-011
• Description: MCU, MPU & DSP Development Tools PCI Express Dev Kit
• Manufacturer: Lattice
• Series: ECP2r

Specifications of DK-PCIE-ECP2M-011

• Silicon Manufacturer: Lattice Semiconductor
• Silicon Family Name: LatticeECP2M
• Kit Contents: Board, IspDOWNLOAD Cable, Power Supply
• Features: Logic Analyzer Connector, On-Board 256 MB DDR2 Memory
• Svhc: No
• Rohs Compliant: Yes
• Main Purpose: Interface, Connectivity
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: LFE2M50E-6FN672C
• Primary Attributes: x1/x4 PCI Express Edge Connectors, 256 MB DDRD Memory
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 10. x4 PCI Express Connections
Table 7. 100MHz Clock Destinations
SERDES
(see Appendix A, Figure 25)
SERDES/FPGA Reference Clocks
The 50-ohm terminated SMA connectors are optionally provided to supply reference clocks directly to the
LatticeECP2M device. Please contact the factory for information to populate the PCB with SMA connectors.
Table 8. SMA Inputs for External Clock Source
SERDES PCI Express Channels
(see Appendix A, Figure 25)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1 or CN2) that fit directly into a PCI Express host receptacle. Power can be supplied directly from the
PCI Express host via the edge-finger connections.
Table 9. x1 PCI Express Connections
L_HDOUTP_0
L_HDOUTN_0
L_HDINP_0
L_HDINN_0
L_REFCLKP
L_REFCLKN
PCIE_PERSETN
U_HDOUTP_3
U_HDOUTN_3
U_HDINP_3
U_HDINN_3
U_HDOUTP_2
U_HDOUTN_2
U_HDINP_2
U_HDINN_2
CML Pin Name
CML Pin Name
FPGA Pin
FPGA Pin
AF21
AE21
AF24
AE24
AC19
AB19
Connector
C12
A17
B17
A14
B14
A18
B18
A15
B15
Clock Destination
J8
J9
CPLD
FPGA
FPGA
FPGA
PCIe_CLKp
PCIe_CLKn
PERSTN
PERp0
PERn0
PETp0
PETn0
PCIE
PERp0
PERn0
PERp1
PERn1
PETp0
PETn0
PETp1
PETn1
PCIE
FPGA_SMA_REFCLKP
FPGA_SMA_REFCLKN
PCI Express Edge
PCB Designation
SERDES Signal
PCI Express Edge
A16
A17
B14
B15
A13
A14
A11
U13
U1
U1
U1
16
A16
A17
B14
B15
A21
A22
B19
B20
LatticeECP2M PCI Express Solutions Board
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
W4-LLM0_GPLL
Destination Pin
P1- LLM2_SPLL
P3- PCLK6_0
A8
FPGA Pin
Description
N25
N24
Description
User’s Guide