74CBTLV16211DGV NXP Semiconductors, 74CBTLV16211DGV Datasheet
74CBTLV16211DGV
Specifications of 74CBTLV16211DGV
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74CBTLV16211DGV Summary of contents
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Rev. 5 — 30 December 2010 1. General description The 74CBTLV16211 provides a dual 12-bit high-speed bus switch with separate output enable inputs (1OE, 2OE). The low on-state resistance of the switch allows connections to be ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range 40 C to +125 C 74CBTLV16211DGG 40 C to +125 C 74CBTLV16211DGV 4. Functional diagram 1A0 2 56 1OE 54 1B0 2A0 15 55 2OE 41 2B0 Fig 1. Logic symbol Fig 2. Logic diagram (one switch) 74CBTLV16211 ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 3. Pin configuration (SOT364-1 and SOT481-2) 5.2 Pin description Table 2. Pin description Symbol Pin n.c. 1 1A0 to 1A11 10, 11, 12, 13, 14 2A0 to 2A11 15, 16, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28 GND 8, 19, 38 2B0 to 2B11 41, 40, 39, 37, 36, 35, 34, 33, 32, 31, 30, 29 ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin 1B0 to 1B11 54, 53, 52, 51, 50, 48, 47, 46, 45, 44, 43, 42 2OE 55 1OE 56 6. Functional description [1] Table 3. Function table Output enable input [ HIGH voltage level LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage input leakage pin nOE current OFF-state V = 3.6 V; see S(OFF) CC leakage current ...
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... NXP Semiconductors 9.2 ON resistance Table 7. Resistance recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions R ON resistance see Figure see Figure [1] Typical values are measured at T [2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two ( terminals ...
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... NXP Semiconductors (Ω (1) 5 (2) (3) ( 0.5 1.0 = 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 8. ON resistance as a function of input voltage 2 (Ω) 6 (1) (2) ( 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = ...
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... NXP Semiconductors = 125 C. (1) T amb = 85 C. (2) T amb = 25 C. (3) T amb = 40 C. (4) T amb Fig 12. ON resistance as a function of input voltage; V 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 15 Symbol Parameter Conditions t propagation delay nAn to nBn or nBn to pd nAn ...
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... NXP Semiconductors 11. Waveforms Measurement points are given in Logic levels: V and Fig 13. The data input (nAn or nBn) to output (nBn or nAn) propagation delays Table 9. Measurement points Supply voltage Input 2 2.7 V 0. 3.6 V 0.5V CC nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 15. Test circuit for measuring switching times Table 10. ...
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... NXP Semiconductors 12. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP56: plastic thin shrink small outline package; 56 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date 74CBTLV16211 v.5 20101230 • Modifications: Section 74CBTLV16211 v ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74CBTLV16211 Product data sheet 15 ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics 9.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 ON resistance test circuit and graphs Dynamic characteristics ...