AD5421BREZ Analog Devices Inc, AD5421BREZ Datasheet - Page 24

• Manufacturer Part Number: AD5421BREZ
• Description: 16bit Linearity Dac With Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5421BREZ

• Settling Time: 50µs
• Number Of Bits: 16
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5421
SERIAL INTERFACE
The AD5421 is controlled by a versatile, 3-wire serial interface
that operates at clock rates up to 30 MHz. It is compatible with
the SPI, QSPI™, MICROWIRE®, and DSP standards. Figure 2
shows the timing diagram. The interface operates with either
a continuous or noncontinuous gated burst clock.
The write sequence begins with a falling edge of the SYNC
signal; data is clocked in on the SDIN data line on the falling
edge of SCLK. On the rising edge of SYNC , the 24 bits of data
are latched; the data is transferred to the addressed register and
the programmed function is executed (either a change in DAC
output or mode of operation).
If packet error checking on the SPI interface is required using
cyclic redundancy codes, an additional eight bits must be written
to the AD5421, creating a 32-bit serial interface. In this case, 32
bits are written to the AD5421 before SYNC is brought high.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (32 bits wide if CRC error
checking of the data is required). Data is loaded into the device
MSB first as a 24-/32-bit word under the control of a serial clock
input, SCLK. The input shift register consists of an 8-bit address/
command byte, a 16-bit data-word, and an optional 8-bit CRC,
as shown in Table 12 and Table 13.
Table 12. Input Shift Register
Table 13. Input Shift Register with CRC
MSB
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
D23
D22
Address/command byte
D21
Address/command byte
D20
D19
D18
D17
D16
D15
D14
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D13
Data-word
D12
The address/command byte decoding is described in Table 11.
Table 11. Address/Command Byte Functions
Address/Command Byte
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
10000001
10000010
10000011
10000100
10000101
REGISTER READBACK
To read back a register, Bit D11 of the control register must be set
to Logic 1 to disable the automatic readback of the fault register.
D11
D10
D9
Data-word
D8
D7
Write to control register
Function
Write to DAC register
Write to offset adjust register
Write to gain adjust register
Load DAC
Force alarm current
Reset
Initiate V
No operation
Read DAC register
Read control register
Read offset adjust register
Read gain adjust register
Read fault register
D6
D5
LOOP
D4
/temp measurement
D3
CRC
D2
D1
LSB
LSB
D0