AD5421BREZ Analog Devices Inc, AD5421BREZ Datasheet - Page 7

• Manufacturer Part Number: AD5421BREZ
• Description: 16bit Linearity Dac With Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5421BREZ

• Settling Time: 50µs
• Number Of Bits: 16
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC PERFORMANCE CHARACTERISTICS
Loop voltage = 24 V; REFIN = 2.5 V external; R
Table 3.
Parameter
DYNAMIC PERFORMANCE
1
TIMING CHARACTERISTICS
Loop voltage = 24 V; REFIN = 2.5 V external; R
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
Table 5. SPI Watchdog Timeout Periods
T0
0
0
0
0
1
1
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
Temperature range: −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 2 and Figure 3.
Specifications guaranteed by design and characterization; not production tested.
Loop Current Settling Time
Loop Current Slew Rate
AC Loop Voltage Sensitivity
Parameter
T1
0
0
1
1
0
0
1
1
1
1, 2, 3
1
T2
0
1
0
1
0
1
0
1
Limit at T
33
17
17
17
10
25
5
5
25
10
70
0
70
R
MIN
Min
43
87
436
873
1746
2619
3493
4366
= t
F
, T
= 5 ns (10% to 90% of DV
MAX
Min
Unit
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns min
μs min
ns min
ns max
ns min
ns max
L
L
50
100
500
1000
2000
3000
4000
5000
Typ
= 250 Ω; all specifications T
= 250 Ω; all specifications T
Typ
50
400
1.3
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
SCLK rising edge to SDO valid (C
SYNC falling edge to SCLK rising edge setup time
SYNC rising edge to SDO tristate (C
DD
) and timed from a voltage level of 1.2 V.
Rev. 0 | Page 7 of 32
Max
59
117
582
1163
2326
3489
4652
5814
Max
MIN
MIN
to T
Unit
μs
μA/μs
μA/V
to T
ms
ms
ms
ms
ms
ms
ms
ms
Unit
MAX
MAX
L SDO
, unless otherwise noted.
.
L SDO
= 30 pF)
Test Conditions/Comments
To 0.1% FSR, C
C
1200 Hz to 2200 Hz, 5 V p-p, R
= 30 pF)
IN
= open circuit
IN
= open circuit
L
= 3 kΩ
AD5421