AD9518-4A/PCBZ Analog Devices Inc, AD9518-4A/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9518-4A/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-4A/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9518-4A
• Primary Attributes: 2 Inputs, 14 Outputs, 1.6GHz VCO
• Secondary Attributes: LVPECL Output Logic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-4
VCO calibration must be manually initiated. This allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it happen every time
the values of certain PLL registers change. For example, this
allows for the VCO frequency to be changed by small amounts
without having an automatic calibration occur each time; this
should be done with caution and only when the user knows the
VCO control voltage is not going to exceed the nominal best
performance limits. For example, a few 100 kHz steps are fine, but
a few MHz might not be. In addition, because the calibration
procedure results in rapid changes in the VCO frequency, the
distribution section is automatically placed in SYNC until the
calibration is finished. Therefore, this temporary loss of outputs
must be expected.
A VCO calibration should be initiated under the following
conditions:
•
•
CLOCK DISTRIBUTION
A clock channel consists of a pair of outputs that share a
common divider. The AD9518 has three channels, each with
two LVPECL outputs, for a total of six LVPECL outputs.
Each channel has its own programmable divider that divides
the clock frequency that is applied to its input. The channel
dividers can divide by any integer from 2 to 32, or the divider
can be bypassed to achieve a divide-by-one.
Because the internal VCO frequency is above the maximum
channel divider input frequency (1600 MHz), the VCO divider
must be used after the on-chip VCO. The VCO divider can be
set to divide by 2, 3, 4, 5, or 6. External clock signals connected
to the CLK input also require the VCO divider if the frequency
of the signal is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for
N + 1 input clock cycles and low for M + 1 input clock cycles
(where D = N + M + 2). For example, a divide-by-5 can be high
for one divider input cycle and low for four cycles, or a divide-
by-5 can be high for three divider input cycles and low for two
cycles. Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
After changing any of the PLL R, P, B, and A divider
settings, or after a change in the PLL reference clock
frequency. This, in effect, means any time a PLL register
or reference clock is changed such that a different VCO
frequency results.
Whenever system calibration is desired. The VCO is
designed to operate properly over extremes of temperatures
even when it is first calibrated at the opposite extreme.
However, a VCO calibration can be initiated at any time,
if desired.
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caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or to start low.
Internal VCO or External CLK as Clock Source
The clock distribution of the AD9518 has two clock input sources:
an internal VCO or an external clock connected to the CLK/ CLK
pins. Either the internal VCO or CLK must be chosen as the source
of the clock signal to distribute. When the internal VCO is selected
as the source, the VCO divider must be used. When CLK is
selected as the source, it is not necessary to use the VCO divider
if the CLK frequency is less than the maximum channel divider
input frequency (1600 MHz); otherwise, the VCO divider must
be used to reduce the frequency to one that can be accepted by
the channel dividers.
VCO divider are selected. Register 0x1E1[1:0] selects the
channel divider source and determines whether the VCO
divider is used. It is not possible to select the VCO without
using the VCO divider.
Table 29. Selecting VCO or CLK as Source for Channel
Divider, and Whether VCO Divider Is Used
1
0
0
1
1
CLK or VCO Direct to LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs, OUT0 to OUT5. This configuration
can pass frequencies up to the maximum frequency of the VCO
directly to the LVPECL outputs. The LVPECL outputs may not
be able to provide a full voltage swing at the highest frequencies.
To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
source for the direct-to-output routing.
Table 30. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
0x1E1[1:0] = 00b
0x1E1[1:0] = 10b
0x192[1] = 1b
0x195[1] = 1b
0x198[1] = 1b
Register 0x1E1
0
0
1
0
1
Channel Divider Source
CLK
CLK
VCO
Not allowed
Table 29
Selection
CLK is the source; VCO divider selected
VCO is the source; VCO divider selected
Direct to output OUT0, OUT1
Direct to output OUT2, OUT3
Direct to output OUT4, OUT5
shows how the VCO, CLK, and
VCO Divider
Used
Not used
Used
Not allowed