AD9518-4A/PCBZ Analog Devices Inc, AD9518-4A/PCBZ Datasheet - Page 61

• Manufacturer Part Number: AD9518-4A/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-4A/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9518-4A
• Primary Attributes: 2 Inputs, 14 Outputs, 1.6GHz VCO
• Secondary Attributes: LVPECL Output Logic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9518 provide the lowest jitter
clock signals available from the AD9518. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 42 shows the LVPECL output stage.
In most applications, a LVPECL far-end Thevenin termination
(see Figure 52) or Y-termination (see Figure 53) is recommended.
In both cases, V
VS_LVPECL. If not, ac coupling is recommended (see
Figure 54).
Figure 52. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_LVPECL
VS_LVPECL
LVPECL
LVPECL
Figure 53. DC-Coupled 3.3 V LVPECL Y-Termination
S
of the receiving buffer should match the
(NOT COUPLED)
SINGLE-ENDED
Z
Z
0
0
50Ω
50Ω
= 50Ω
= 50Ω
127Ω
83Ω
VS_DRV
50Ω
127Ω
83Ω
50Ω
50Ω
V
S
LVPECL
LVPECL
= 3.3V
V
S
Rev. A | Page 61 of 64
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
where VS_LVPECL = 2.5 V, the 50 Ω termination resistor
connected to ground in Figure 53 should be changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below V
driver. In this case, VS_LVPECL on the AD9518 should equal
V
shown results in a dc bias point of VS_LVPECL − 2 V, the actual
common-mode voltage is VS_LVPECL − 1.3 V because there is
additional current flowing from the AD9518 LVPECL driver
through the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the
pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.
S
of the receiving buffer. Although the resistor combination
VS_LVPECL
Figure 54. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL
200Ω
0.1nF
0.1nF
200Ω
TRANSMISSION LINE
100Ω DIFFERENTIAL
(COUPLED)
100Ω
OL
AD9518-4
of the LVPECL
LVPECL
V
S