AD9518-4A/PCBZ Analog Devices Inc, AD9518-4A/PCBZ Datasheet - Page 37

• Manufacturer Part Number: AD9518-4A/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-4A/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9518-4A
• Primary Attributes: 2 Inputs, 14 Outputs, 1.6GHz VCO
• Secondary Attributes: LVPECL Output Logic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Synchronization of the outputs is executed in several ways.
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The most common way to execute the SYNC function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
IINPUT TO CHANNEL DIVIDER
SYNC PIN
SYNC PIN
INPUT TO CHANNEL DIVIDER
INPUT TO VCO DIVIDER
CHANNEL DIVIDER
The SYNC pin is forced low and then released (manual sync).
By setting and then resetting any one of the following three
bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the power down
distribution reference bit (Register 0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
The RESET pin is forced low and then released (chip reset).
The PD pin is forced low, then released (chip power-down).
When a VCO calibration is completed, an internal SYNC
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
OUTPUT CLOCKING
CHANNEL DIVIDER
CHANNEL DIVIDER
INPUT TO CLK
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT OF
OUTPUT OF
Figure 40. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
Figure 41. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
1
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
2
2
3
3
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER OUTPUT STATIC
Rev. A | Page 37 of 64
4
4
5
5
6
6
low and then released when synchronization is desired. The
timing of the SYNC operation is shown in
VCO divider) and
an uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the AD9518. The
delay from the
output clocking is between 14 and 15 cycles of clock at the channel
divider input, plus either one cycle of the VCO divider input
(see
depending on whether the VCO divider is used. Cycles are
counted from the rising edge of the signal.
Another common way to execute the SYNC function is by setting
and resetting the soft SYNC bit at Register 0x230[0] (see Table 43
through Table 49 for details). Both setting and resetting of the
soft SYNC bit require an update all registers (Register 0x232[0] = 1)
operation to take effect.
7
Figure 40
7
8
8
9
), or one cycle of the CLK input (see
9
SYNC rising edge to the beginning of synchronized
10
Figure 41
10
11
11
12
(VCO divider not used). There is
12
13
13
14
14
1
1
Figure 40
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
AD9518-4
Figure 41
(using the
),