AD9518-4A/PCBZ Analog Devices Inc, AD9518-4A/PCBZ Datasheet - Page 35

• Manufacturer Part Number: AD9518-4A/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-4A/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9518-4A
• Primary Attributes: 2 Inputs, 14 Outputs, 1.6GHz VCO
• Secondary Attributes: LVPECL Output Logic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, 6) and the
division of the channel divider. Table 31 indicates how the
frequency division for a channel is set.
Table 31. Frequency Division for Divider 0 to Divider 2
CLK or VCO
Selected
CLK/VCO
CLK/VCO
CLK/VCO
CLK
CLK
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 42 through Table 49).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Table 47, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are three channel dividers (0, 1, and 2) driving a total of
six LVPECL outputs (OUT0 to OUT5). Table 32 gives the
register locations used for setting the division and other
functions of these dividers. The division is set by the values of
M and N. The divider can be bypassed (equivalent to divide-by-1,
divider circuit is powered down) by setting the bypass bit. The
duty-cycle correction can be enabled or disabled according to
the setting of the DCCOFF bits.
Table 32. Setting D
Divider
0
1
2
1
Note that the value stored in the register = # of cycles minus 1.
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
VCO
Divider
2 to 6
2 to 6
2 to 6
Not used
Not used
X
for Divider 0, Divider 1, and Divider 2
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
Channel
Divider
1 (bypassed)
1 (bypassed)
2 to 32
1 (bypassed)
2 to 32
Bypass
0x191[7]
0x194[7]
0x197[7]
Direct to
Output
Yes
No
No
No
No
Frequency
Division
(2 to 6) ×
(2 to 32)
1
2 to 32
1
(2 to 6) × (1)
DCCOFF
0x192[0]
0x195[0]
0x198[0]
Rev. A | Page 35 of 64
1
Channel Frequency Division (0, 1, and 2)
For each channel (where the channel number is x: 0, 1, or 2),
the frequency division, D
(four bits each, representing Decimal 0 to Decimal 15), where
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, D
Otherwise, D
each channel divider to divide by any integer from 2 to 32.
Duty Cycle and Duty-Cycle Correction (0, 1, and 2)
The duty cycle of the clock signal at the output of a channel is
a result of some or all of the following conditions:
•
•
•
•
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
•
•
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percentage (%).
The duty cycle at the output of the channel divider for various
configurations is shown in Table 33 to Table 35.
Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, Odd
Even, Odd
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle? (The internal VCO has
a 50% duty cycle.)
An even division must be set as M = N.
An odd division must be set as M = N + 1.
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
X
= (N + 1) + (M + 1) = N + M + 2. This allows
D
X
X
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
, is set by the values of M and N
X
= 1.
Output Duty Cycle
DCCOFF = 0
50%
50%
50%
50%; requires M = N
50%; requires M = N + 1
AD9518-4