AD9518-4A/PCBZ Analog Devices Inc, AD9518-4A/PCBZ Datasheet - Page 58

• Manufacturer Part Number: AD9518-4A/PCBZ
• Description: 6-Output Clock Generator With 2.8GHz
• Manufacturer: Analog Devices Inc

Specifications of AD9518-4A/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9518-4A
• Primary Attributes: 2 Inputs, 14 Outputs, 1.6GHz VCO
• Secondary Attributes: LVPECL Output Logic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9518-4
Reg.
Addr.
(Hex)
0x196
0x197
0x198
Table 47. VCO Divider and CLK Input
Reg.
Addr
(Hex)
0x1E0
0x1E1
Bits
[7:4]
[3:0]
7
6
5
4
[3:0]
1
0
Bits
[2:0]
4
3
2
Name
VCO divider
Power down clock input section
Power down VCO clock interface
Power down VCO and CLK
Name
Divider 2 low cycles
Divider 2 high cycles
Divider 2 bypass
Divider 2 nosync
Divider 2 force high
Divider 2 start high
Divider 2 phase offset
Divider 2 direct to output
Divider 2 DCCOFF
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; route input to divider output.
0: uses divider (default).
1: bypasses divider.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Select clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Description
2
0
0
0
0
1
1
1
1
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
1
0
0
1
1
0
0
1
1
Rev. A | Page 58 of 64
0
0
1
0
1
0
1
0
1
Divide
2.
3.
4 (default).
5.
6.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.