AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 15

• Manufacturer Part Number: AD9520-5BCPZ
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER DISSIPATION
Table 15.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
On/Off
Power-On Default
Distribution Only Mode; VCO Divider On;
Distribution Only Mode; VCO Divider Off;
Maximum Power, Full Operation
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
VCO Divider On/Off
REFIN (Differential) Off
REF1, REF2 (Single-Ended) On/Off
PLL Dividers and Phase Detector
LVPECL Channel
LVPECL Driver
CMOS Channel
CMOS Driver On/Off
Channel Divider Enabled
Zero Delay Block On/Off
One LVPECL Output Enabled
One LVPECL Output Enabled
Min
Typ
1.32
0.39
0.36
1.4
60
24
4
32
25
15
51
121
51
145
11
40
30
Max
1.5
0.46
0.42
1.7
80
33
4.8
40
30
20
63
144
73
180
24
57
34
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Unit
W
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
Does not include power dissipated in external resistors; all
LVPECL outputs terminated with 50 Ω to V
outputs have 10 pF capacitive loading; VS_DRV = 3.3 V
No clock; no programming; default register values
f
output and output divider enabled; zero delay off
f
LVPECL output and output divider enabled; zero delay off
PLL on; VCO divider = 2; all channel dividers on; 12 LVPECL
outputs @ 125 MHz; zero delay on
PD pin pulled low; does not include power dissipated in
termination resistors
PD pin pulled low; PLL power-down, 0x010[1:0] = 01b;
power-down SYNC, 0x230[2] = 1b; power-down distribution
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
Delta between reference input off and differential reference
input mode
Delta between reference inputs off and one singled-ended
reference enabled; double this number if both REF1 and REF2
are powered up
PLL off to PLL on, normal operation; no reference enabled
No LVPECL output on to one LVPECL output on; channel divider
set to 1
Second LVPECL output turned on, same channel
No CMOS output on to one CMOS output on; channel divider
set to 1; f
Additional CMOS outputs within the same channel turned on
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
reference, 0x230[1] = 1b
CLK
CLK
= 2.4 GHz; f
= 2.4 GHz; f
OUT
= 62.5 MHz and 10 pF of capacitive loading
OUT
OUT
= 200 MHz; VCO divider = 2; one LVPECL
= 200 MHz; VCO divider bypassed; one
CC
− 2 V; all CMOS
AD9520-5