AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 17

• Manufacturer Part Number: AD9520-5BCPZ
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 18. Pin Function Descriptions
Pin No.
1, 11, 12, 32,
40, 41,49,
57, 60, 61
2
3
4
5
6
7
8
9, 10
13
14
Input/
Output
I
O
O
I
O
O
I
I
I
I
Pin
Type
Power
3.3 V CMOS
3.3 V CMOS
Power
Loop filter
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Differential
clock input
Differential
clock input
SCLK/SCL
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
REF_SEL
REFMON
STATUS
SYNC
Mnemonic
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
NC
CLK
CLK
VCP
CLK
CLK
NC
NC
VS
LD
CP
VS
VS
CS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Description
3.3 V Power Pins.
Reference Monitor (Output). This pin has multiple selectable outputs.
Lock Detect (Output). This pin has multiple selectable outputs.
Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. VCP must still be connected
to 3.3 V if the PLL is not used.
Charge Pump (Output). This pin connects to an external loop filter. This pin can
be left unconnected if the PLL is not used.
Programmable Status Output.
Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronization and Manual Holdover. This pin initiates a manual
synchronization and is used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
No Connect. These pins can be left floating.
Along with CLK, this pin is the differential input for the clock distribution section.
Along with CLK, this pin is the differential input for the clock distribution section. If a
single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor
from CLK to ground.
Figure 5. Pin Configuration
Rev. 0 | Page 17 of 80
(Not to Scale)
AD9520-5
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT3 (OUT3A)
OUT3 (OUT3B)
VS_DRV
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
VS
OUT8 (OUT8B)
OUT8 (OUT8A)
OUT7 (OUT7B)
OUT7 (OUT7A)
VS_DRV
OUT6 (OUT6B)
OUT6 (OUT6A)
AD9520-5