AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 64

• Manufacturer Part Number: AD9520-5BCPZ
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
017
018
018
018
018
019
019
019
AD9520-5
[1:0] Antibacklash
[7]
[6:5] Lock detect
[4]
[3]
[7:6] R, A, B counters
[5:3] R path delay
[2:0] N path delay
pulse width
Enable CMOS
reference input
dc offset
counter
Digital lock
detect window
Disable digital
lock detect
SYNC pin reset
Description
[7]
1
1
1
1
1
1
1
1
1
1
1
1
[1]
0
0
1
1
Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.
[7] = 0; disable dc offset (default).
[7] = 1; enable dc offset.
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
a locked condition.
[6]
0
0
1
1
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time,
the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock
threshold.
[4] = 0; high range (default).
[4] = 1; low range.
Digital lock detect operation.
[3] = 0; normal lock detect operation (default).
[3] = 1; disable lock detect.
[7]
0
0
1
1
R path delay, see Table 2 (default: 0x0).
N path delay, see Table 2 (default: 0x0).
[6] [5]
1
1
1
1
1
1
1
1
1
1
1
1
[0] Antibacklash Pulse Width (ns)
0
1
0
1
[5] PFD Cycles to Determine Lock
0
1
0
1
[6]
0
1
0
1
0
0
0
0
1
1
1
1
1
1
1
1
2.9 (default)
1.3
6.0
2.9
5 (default)
16
64
255
Action
Do nothing on SYNC (default).
Asynchronous reset.
Synchronous reset.
Do nothing on SYNC.
[4]
1
1
1
1
0
0
0
0
1
1
1
1
[3]
0
0
1
1
0
0
1
1
0
0
1
1
Rev. 0 | Page 64 of 80
[2]
0
1
0
1
0
1
0
1
0
1
0
1
Level or
Dynamic
Signal
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at STATUS Pin
Unselected reference to PLL (not available when in
differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (Status of selected reference) AND (status of VCO).
Status of CLK frequency (active low).
Selected reference (low = REF2, high = REF1).
DLD (active low).
Holdover active (active low).
LD pin comparator output (active low).