AD9520-5BCPZ Analog Devices Inc, AD9520-5BCPZ Datasheet - Page 38

• Manufacturer Part Number: AD9520-5BCPZ
• Description: 12/24-Output Clock Generator
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-5BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.6GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-5
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input.
The zero delay function of the AD9520-5 is achieved by feeding
the output of Channel Divider 0 back to the PLL N divider. In
Figure 36, the change in signal routing for zero delay mode is
shown in blue.
Set Register 0x01E[1] = 1b to select zero delay mode. In the zero
delay mode, the output of Channel Divider 0 is routed back to the
PLL (N divider) through Mux1 (feedback path shown in blue in
Figure 36). The PLL synchronizes the phase/edge of the output of
Channel Divider 0 with the phase/edge of the reference input.
CLK/CLK
REFIN/
REFIN
MUX1
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
0
DIVIDER
DIVIDER
REG 0x01E[1] = 1
R
N
EXTERNAL VCXO
DELAY
DELAY
R
N
Figure 36. Zero Delay Function
INTERNAL ZERO DELAY CLOCK FEEDBACK PATH
Rev. 0 | Page 38 of 80
PFD
CP
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input. Both the R delay and the N delay inside the
PLL can be programmed to compensate for the propagation
delay from the output drivers and PLL components to minimize
the phase offset between the clock output and the reference
input to achieve zero delay.
CHANNEL DIVIDER 0
CHANNEL DIVIDER 1
CHANNEL DIVIDER 2
CHANNEL DIVIDER 3
AD9520-5
OUT0 TO OUT2
OUT3 TO OUT5
OUT6 TO OUT8
OUT9 TO OUT11
FILTER
LOOP