AD9963BCPZRL Analog Devices Inc, AD9963BCPZRL Datasheet - Page 24

• Manufacturer Part Number: AD9963BCPZRL
• Description: Dual 16B, 200 MSPS D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9963BCPZRL

• Package / Case: 72-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9961/AD9963
Addr
CONFIGURATION REGISTER BIT DESCRIPTIONS
Table 15.
Register Name
Serial Port Config
ADC Address
CM Buffer Enable
ADC Offset
Digital Filters
0x7A
0x7D
0x71
0x72
0x75
0x77
0x78
0x79
0x7B
0x7E
0x7F
0x80
0x81
0x82
0xFF
Default
Varies
Varies
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Bit 7
ADCCLKSEL
DLL_Locked
AUXADC_EN
TMPSNS_EN
Unused
Register
Address
0x00
0x05
0x0F
0x10
0x30
CONV_TIME[1:0]
Bit(s)
7, 0
6, 1
5, 2
1:0
1
5:0
7:6
5
4
3
Bit 6
DACCLKSEL
AUXADC_RESB
RXTrim_EN
Unused
Parameter
SDIO
LSB_First
RESET
ADDRQ, ADDRI
RXCML
ADC_OFFSET[5:0]
Unused
DEC_BP
INT1_BP
INT0_BP
AUXADC[3:0]
Unused
DLLDIV
0
Bit 5
Unused
RXTrim_Fine
Unused
Unused
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Bit 4
DLL_REF_EN
AUXCML_EN
Function
0: use SDIO pin as input data only.
1: use SDIO as both input and output data.
0: first bit of serial data is MSB of data byte.
1: first bit of serial data is LSB of data byte.
A transition from 0 to 1 on this bit resets the device. All registers but
Register 0x00 revert to their default values.
Bits are set to determine which device on chip receives ADC specific
write commands. ADC specific write commends include writes to
Registers 0x0F and Register 0x10. These writes also require a rising end
on the Update bit (Register 0xFF, Bit 0).
00: no ADCs are addressed.
01: I ADC is addressed.
10: Q ADC is addressed
11: both I and Q ADCs are addressed.
Enable control for the RXCML output buffer.
Note that updating this bit also requires writing to Register 0x05 and
Register 0xFF as described in the Sub Serial Interface Communications
section.
0: RXCML pin is high impedance.
1: RXCML pin is a low impedance 1.4 V output.
Adds a dc offset to the ADC output of whichever ADC is addressed by
Register 0x05. The offset applied is as follows:
011111: offset = +31 LSBs
…
000001: offset = +1 LSB
000000: offset = 0 LSB
111111: offset = −1 LSB
…
100000: offset = −32 LSBs
1: bypass 2× decimator in Rx path (D0).
1: bypass 2× Half-Band Interpolation Filter 1 (INT1).
1: bypass 2× Half-Band Interpolation Filter 0 (INT0).
Unused
Unused
Unused
AUXADC[11:4]
RXQ_Trim[9:2]
RXI_Trim[9:2]
AUXREF_ADJ[2:0]
Bit 3
DLL_RESB
CONV_COMPL
RX_FSADJ[4:0]
Bit 2
M[4:0]
0
RXQ_Trim[1:0]
RXI_Trim[1:0]
N[3:0]
AUXADC_CH[2:0]
CHAN_SEL[2:0]
Bit 1
AUXDIV[2:0]
0
Unused
Bit 0
RX_DC
GAINCAL_
ENI
GAINCAL_
ENQ
Update