AD9963BCPZRL Analog Devices Inc, AD9963BCPZRL Datasheet - Page 49

• Manufacturer Part Number: AD9963BCPZRL
• Description: Dual 16B, 200 MSPS D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9963BCPZRL

• Package / Case: 72-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In addition to the different timing modes listed in Figure 75 to
Figure 78, the input data can also be delivered from the device
in either unsigned binary or twos complement format. The
format type is chosen via the RX_BNRY configuration bit.
TRXD[11:0]
TRXD[11:0]
TRXD[11:0]
TRXD[11:0]
TRXCLK
TRXCLK
TRXCLK
TRXCLK
TRXIQ
TRXIQ
TRXIQ
TRXIQ
Figure 76. Rx Timing, Q ADC Only, Bus Rate Clock Mode
Figure 75. Rx Timing, I ADC Only, Bus Rate Clock Mode
Figure 78. Rx Timing, Q ADC Only, DDR Clock Mode
Figure 77. Rx Timing, I ADC Only, DDR Clock Mode
Q0
I0
Q0
I0
t
t
t
OD2
OD2
OD2
t
OD2
Q1
I1
Q1
I1
Rev. 0 | Page 49 of 60
TX PORT OPERATION (FULL-DUPLEX MODE)
The Tx port operates with a qualifying clock that can be
configured as either an input or an output. The input data
(TXD[11:0]) must be accompanied by the TXIQ signal which
identifies to which transmit channel (I or Q) the data is
intended. By default, the data and TXIQ signals are latched by
the device on the rising edge of TXCLK. The timing diagram is
shown in Figure 79
The setup and hold time requirements for the Tx port in data
rate clock mode are given in Table 24.
The input samples to the device are assembled to create a
quadrature pair of data. The data can be arranged in two
possible data pairing orders and with two possible data to TXIQ
signal phase relationships. This creates four possible timing
modes. The AD9961/AD9963 can be configured to accept data
in any of these four modes. The data pairing order is controlled
by the TX_IFIRST bit. The data to TXIQ phase relationship is
controlled by the TXIQ_HILO bit. The two programming
options produce the four timing diagrams shown in Figure 80.
In addition to the different timing modes listed above, the input
data can also be accepted by the device in either unsigned
binary or twos complement format. The format type is chosen
via the TX_BNRY configuration bit.
TXD[11:0]
TXD[11 :0]
TXD[11 :0]
TXD[11 :0]
TXD[11 :0]
TXCLK
TXIQ
TXIQ
Figure 79. Tx Port Timing Diagram (Data Rate Clock Mode)
Figure 80. Transmit Path Data Pairing Options
Q0
Q0
I0
I0
Q0
Q1
I1
I0
t
SU
Q1
Q1
I1
I1
t
HD
Q1
Q2
I2
I1
AD9961/AD9963
Q2
Q2
I2
I2
Q2
Q3
I3
I2
TX_IFIRST = 1
TXIQ_HILO = 1
TX_IFIRST = 1
TXIQ_HILO = 0
TX_IFIRST = 0
TXIQ_HILO = 1
TX_IFIRST = 0
TXIQ_HILO = 0