AD9963BCPZRL Analog Devices Inc, AD9963BCPZRL Datasheet - Page 32

• Manufacturer Part Number: AD9963BCPZRL
• Description: Dual 16B, 200 MSPS D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9963BCPZRL

• Package / Case: 72-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9961/AD9963
Register Name
DLL Control 0
DLL Control 1
DLL Control 2
Aux ADC Config
and Conversion
Start
Register
Address
0x71
0x72
0x75
0x77
Bit(s)
7
6
5
4
3:0
7
6:5
4:0
7:4
3
2:0
7:6
5:3
2:0
CONV_TIME[1:0]
Parameter
ADCCLKSEL
DACCLKSEL
Unused
DLL_REF_EN
N[3:0]
DLL_Locked
DLLDIV[1:0]
M[4:0]
0
DLL_RESB
0
Unused
AUXADC_CH[2:0]
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Function
100000: V
100001: V
…
111111 : V
1: selects DLL output as the ADC sampling clock.
0: selects external clock as the ADC sampling clock.
1: selects DLL output as the DAC sampling clock.
0: selects external clock as the DAC sampling clock.
1: enables the input reference clock to the DLL.
Sets DLL divide ratio (1 to 8) at the output of the DLL.
0000: not valid.
0001: 1.
0010: 2.
…
0110: 6.
0111: not valid.
1000: 8.
1001: not valid.
…
1111: not valid.
1: DLL has locked to reference clock (read only).
00: DLL output is directly driven out. Divider is bypassed.
01: DLL output is directly driven out. Divider is bypassed.
10: DLL output is divided by 2.
11: DLL output is divided by 4.
Sets DLL multiplication factor (1 to 32).
00000: 1.
00001: 2.
…
11111: 32.
Set these bits to 0.
Reset DLL. The DLL must be reset by a low to high transition on this bit
each time the DLL configuration is changed or the reference frequency is
changed.
Set these bits to 0.
Sets the number of AUXADCCLK cycles required to perform a conversion.
00: 20 AUXADCCLK cycles.
01: 22 AUXADCCLK cycles.
10: 26 AUXADCCLK cycles.
11: 34 AUXADCCLK cycles.
Selects analog input channel to the auxiliary ADC.
000: AUXIN1, Pin 72.
001: AUXIO2, Pin 71.
010: AUXIO3, Pin 70.
011: internal VPTAT voltage.
100: internal VCMLI voltage.
101: internal VCMLQ voltage.
REF
REF
REF
= 0.8 V.
= 0.80625 V.
= 0.99375 V.