AD9963BCPZRL Analog Devices Inc, AD9963BCPZRL Datasheet - Page 28

• Manufacturer Part Number: AD9963BCPZRL
• Description: Dual 16B, 200 MSPS D-A Converter
• Manufacturer: Analog Devices Inc

Specifications of AD9963BCPZRL

• Package / Case: 72-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9961/AD9963
Register Name
Rx Data Interface
DAC12 Config
DAC12A MSBs
DAC12A LSBs
DAC12B MSBs
DAC12B LSBs
DAC10B Config
Register
Address
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
Bit(s)
7
6
5
4
3
2
1
0
7
6
5
4
3:2
1
0
7:0
7:4
3:0
7:0
7:4
3:0
7
6:5
4:2
Parameter
Unused
RX_CLK
RX_BUS
SINGLERX
TXCLK_MD
HD_BUSCTL
HD_CLKMD
FULL_DUPLEX
DAC12B_EN
DAC12A_EN
DAC12B_TOP
DAC12A_TOP
Unused
AUXDAC_REF
DAC_UPDATE
DAC12A[11:4]
Unused
DAC12A[3:0]
DAC12B[11:4]
Unused
DAC12B[3:0]
DAC10B_EN
Unused
DAC10B_TOP[2:0]
Rev. 0 | Page 28 of 60
Function
0: when SINGLERX is active, use Q side clock.
1: when SINGLERX is active, use I side clock.
0: when SINGLERX is active, use the Q ADC.
1: when SINGLERX is active, use the I ADC.
0: use both Rx paths.
1: use only one Rx path.
This bit controls the operation of the TXCLK pin when the chip is
configured in half-duplex 1-clock mode. This bit is otherwise ignored.
0: the TXCLK pin is set to a high impedance output.
1: the DLL clock output is driven onto the TXCLK pin.
0: selects SPI mode to control bus direction in half-duplex mode.
1: selects Pin mode to control bus direction in half-duplex mode.
SPI bit to set Tx or Rx is Register 0x30, Bit 0. Register 0x30, Bit 1 is ignored
in this case.
0: selects 1-clock submode if in half-duplex mode.
1: selects 2-clock submode if in half-duplex mode.
0: configures the digital interface for half-duplex mode (covers both 1-
clock and 2-clock submodes).
1: configures the digital interface for full-duplex mode.
0: powers down DAC12B.
1: enables DAC12B.
0: powers down DAC12A.
1: enables DAC12A.
0: sets DAC12B range to 3.3 × V
1: sets DAC12B range to 1.8 × V
0: sets DAC12A range to 3.3 × V
1: sets DAC12A range to 1.8 × V
Selects where the voltage reference for all of the auxiliary DACs is
derived.
0: resistive divider from AUX33V. V
1: selects the 1.0 V bandgap voltage. V
This bit determines which of the two data words updates all four of the
auxiliary DACs.
0: update DACs after LSB write.
1: update DACs after MSB write.
DAC12A voltage control word (upper eight bits).
DAC12A voltage control word (lower four bits).
DAC12B voltage control word (upper eight bits).
DAC12B voltage control word (lower four bits).
0: powers down DAC10B.
1: enables DAC10B.
Sets the DAC output voltage at the top range as follows:
000: 1.0 V.
001: 1.5 V.
AUXDACREF
AUXDACREF
AUXACREF
AUXDACREF
AUXDACREF
.
AUXDACREF
.
.
.
= V
AUX33V
= 1.0 V.
/3.3.