ADF4216BRUZ-RL7 Analog Devices Inc, ADF4216BRUZ-RL7 Datasheet - Page 10

• Manufacturer Part Number: ADF4216BRUZ-RL7
• Description: DUAL PLL,1.2/0.5GHz I.C
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4216BRUZ-RL7

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4216/ADF4217/ADF4218
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
IF/RF INPUT STAGE
The IF/RF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
PRESCALER
The dual modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the IF/RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The prescaler is selectable. On the IF side it can be set to
either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17
(DB20 set to 1). On the RF side it can be set to 64/65 (DB20 of
the RF AB Counter Latch set to 0) or 32/33 (DB20 set to 1).
See Tables IV and VI.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The devices are guaranteed to work when the
prescaler output is 165 MHz or less. Typically they will work
with 200 MHz output from the prescaler.
REF
RF
RF
IN
IN
IN
A
B
GENERATOR
NC
SW1
BIAS
POWER-DOWN
CONTROL
NO
2k
NC
SW3
SW2
2k
100k
AGND
AV
BUFFER
DD
TO
R COUNTER
IN
pin
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
f
P
B
A
f
R
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase fre-
quency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
VCO
REFIN
INPUT STAGE
– IN
FROM IF/RF
IN
HI
HI
= Output frequency of external voltage controlled oscilla-
= Preset modulus of dual modulus prescaler (8/9, 16/17,
= Preset Divide Ratio of binary 11-bit counter (1 to
= Preset Divide Ratio of binary 6-bit A counter (0 to
= Output frequency of the external reference frequency
= Preset divide ratio of binary 14-bit programmable
tor (VCO).
etc.).
2047).
63).
oscillator.
reference counter (1 to 16383).
D1
D1
CLR1
CLR2
U1
U1
MODULUS
CONTROL
DIVIDER
N = BP+A
Q1
Q1
f
VCO
N
PRESCALER
DOWN
UP
P/P+1
= [(P × B) + A] × f
ELEMENT
DELAY
LOAD
LOAD
COUNTER
COUNTER
U3
11-BIT B
6-BIT A
REFIN
/R
CHARGE
PUMP
TO PFD
CP