ADF4216BRUZ-RL7 Analog Devices Inc, ADF4216BRUZ-RL7 Datasheet - Page 17

• Manufacturer Part Number: ADF4216BRUZ-RL7
• Description: DUAL PLL,1.2/0.5GHz I.C
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4216BRUZ-RL7

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IF SECTION
Programmable IF Reference (R) Counter
If control bits C2, C1 are 0, 0 then the data is transferred from
the input shift register to the 14 Bit IF R counter. Table III
shows the input shift register data format for the IF R counter
and the divide ratios possible.
IF Phase Detector Polarity
P1 sets the IF Phase Detector Polarity. When the IF VCO char-
acteristics are positive, this should be set to “1.” When they are
negative, it should be set to “0.” See Table III.
IF Charge Pump Three-State
P2 puts the IF charge pump into three-state mode when pro-
grammed to a “1.” It should be set to “0” for normal operation.
See Table III.
IF Charge Pump Currents
P5 sets the IF Charge Pump current. With P5 set to “0,” I
1.25 mA. With P5 set to “1,” I
Programmable IF AB Counter
If control bits C2, C1 are 0, 1, the data in the input register is
used to program the IF AB counter. The AB counter consists of
a 6-bit swallow counter (A counter) and 11-bit programmable
counter (B counter). Table IV shows the input register data
format for programming the IF AB counter and the divide ratios
possible.
IF Prescaler Value
P6 in the IF AB Counter Latch sets the IF prescaler value.
Either 8/9 or 16/17 is available. See Table IV.
IF Power-Down
Table III and Table V show the power-down bits in the
ADF4216 family. See Power-Down section for functional
description.
RF SECTION
Programmable RF Reference (R) Counter
If control bits C2, C1 are 1, 0, the data is transferred from the
input shift register to the 14-bit RFR counter. Table V shows
the input shift register data format for the RFR counter and the
divide ratios possible.
RF Phase Detector Polarity
P9 sets the IF Phase Detector Polarity. When the RF VCO
characteristics are positive this should be set to “1.” When they
are negative it should be set to “0.” See Table V.
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when pro-
grammed to a “1.” It should be set to “0” for normal operation.
See Table V.
RF Program Modes
Table III and Table V show how to set up the Program Modes
in the ADF4216 family.
RF Charge Pump Currents
P13 sets the RF Charge Pump current. With P13 set to “0,” I
is 1.25 mA. With P5 set to “1,” I
Programmable RF AB Counter
If control bits C2, C1 are 1, 1, the data in the input register is
used to program the RF N (AB) counter. The AB counter con-
sists of a 6-bit swallow counter (A Counter) and an 11-bit
CP
CP
is 4.375 mA. See Table III.
is 4.375 mA. See Table V.
CP
is
CP
programmable counter (B Counter). Table VI shows the input
register data format for programming the RF N counter and the
divide ratios possible.
RF Prescaler Value
P14 in the RF AB Counter Latch sets the RF prescaler value.
Either 32/33 or 64/65 is available. See Table VI.
RF Power-Down
Table IV and Table VI show the power-down bits in the ADF4216
family. See Power-Down section for functional description.
RF Fastlock
The RF CP Gain bit (P17) of the RF N register in the ADF4210
family is the Fastlock Enable Bit. Only when this is “1” is IF
Fastlock enabled. When Fastlock is enabled, the RF CP current
is set to its maximum value. Also an extra loop filter damping
resistor to ground is switched in using the FL
pensating for the change in loop characteristics while in Fastlock.
Since the RF CP Gain bit is contained in the RF N Counter,
only one write is needed both to program a new output fre-
quency and to initiate Fastlock. To come out of Fastlock, the
RF CP Gain bit on the RF N register must be set to “0.” See
Table VI.
APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver
Figure 7 shows the ADF4216 being used in a classic superhet-
erodyne receiver to provide the required LOs (Local Oscillators).
In this circuit, the reference input signal is applied to the circuit
at REF
ture Controlled Crystal Oscillator).
In order to have a channel spacing of 200 kHz (the GSM stan-
dard), the reference input must be divided by 65, using the
on-chip reference counter.
The RF output frequency range is 1050 MHz to 1085 MHz. Loop
filter component values are chosen so that the loop bandwidth is
20 kHz. The synthesizer is set up for a charge pump current of
4.375 mA and the VCO sensitivity is 15.6 MHz/V.
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
Local Oscillator for WCDMA Receiver
Figure 8 shows the ADF4217 being used to generate the local
oscillator frequencies for a Wideband CDMA (WCDMA) system.
The RF output range needed is 1720 MHz to 1780 MHz. The
VCO190–1750T will accomplish this. Channel spacing is 200 kHz
with a 20 kHz loop bandwidth. VCO sensitivity is 32 MHz/V.
Charge pump current of 4.375 mA is used and the desired phase
margin for the loop is 45°.
The IF output is fixed at 200 MHz. The VCO190–200T is
used. It has a sensitivity of 11.5 MHz/V. Channel spacing and
loop bandwidth is chosen to be the same as the RF side.
IN
and is being generated by a 13 MHz TCXO (Tempera-
ADF4216/ADF4217/ADF4218
O
pin, thus com-