ADF4216BRUZ-RL7 Analog Devices Inc, ADF4216BRUZ-RL7 Datasheet - Page 5

• Manufacturer Part Number: ADF4216BRUZ-RL7
• Description: DUAL PLL,1.2/0.5GHz I.C
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4216BRUZ-RL7

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/No
• Frequency - Max: 1.2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No. Mnemonic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
V
CP
DGND
RF
RF
AGND
REF
DGND
MUXOUT
CLK
DATA
LE
AGND
IF
IF
DGND
CP
V
V
DD
P
P
DD
IN
IN
1
2
IN
IN
RF
IF
1
B
A
2
IN
A
B
RF
IF
RF
IF
IF
This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Fre-
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
Function
Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. V
have the same potential as V
Power Supply for the RF Charge Pump. This should be greater than or equal to V
Output from the RF Charge Pump. When enabled this provides ± I
turn drives the external VCO.
Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
Ground Pin for the RF Analog Circuitry.
Reference Input. This is a CMOS input with a nominal threshold of V
tance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
Ground Pin for the IF Digital (Interface and Control Circuitry).
quency to be accessed externally. See Table V.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
Ground Pin for the IF Analog Circuitry.
Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry.
Output from the IF Charge Pump. When enabled this provides ± I
drives the external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to V
Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. V
and 5.5 V. V
DD
2 must have the same potential as V
PIN FUNCTION DESCRIPTIONS
MUXOUT
DGND
AGND
DGND
DD
PIN CONFIGURATION
RF
RF
REF
V
CP
2.
DD
V
IN
IN
RF
RF
RF
P
A
IN
IF
B
1
1
10
1
2
3
4
5
6
7
8
9
ADF4216/
ADF4217/
ADF4218
TSSOP
DD
1 should have a value of between 2.7 V and 5.5 V. V
20
19
18
17
16
15
14
13
12
11
V
V
CP
DGND
IF
IF
AGND
LE
DATA
CLK
DD
DD
P
IN
IN
2
IF
A
B
2
1.
IF
IF
ADF4216/ADF4217/ADF4218
DD
CP
2 should have a value of between 2.7 V
CP
to the external loop filter, which in turn
to the external loop filter, which in
DD
/2 and an equivalent input resis-
DD
DD
.
.
DD
1 must