ADSP-BF512KSWZ-3 Analog Devices Inc, ADSP-BF512KSWZ-3 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF512KSWZ-3
• Description: Low-Power Blackfin Processor
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF512KSWZ-3

• Interface: I²C, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 5. Core Clock Ratios
Table 4. Example System Clock Ratios
The maximum CCLK frequency not only depends on the part's
speed grade (see
voltage. See
(SCLK) depends on the chip package and the applied V
V
BOOTING MODES
The processor has several mechanisms (listed in
automatically loading internal and external memory after a
reset. The boot mode is defined by three BMODE input bits
dedicated to this purpose. There are two categories of boot
modes. In master boot modes the processor actively loads data
from parallel or serial memories. In slave boot modes the pro-
cessor receives data from external host devices.
The boot modes listed in
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time. The BMODE
Signal Name
CSEL1–0
00
01
10
11
Signal Name
SSEL3–0
0010
0110
1010
DDEXT
Table 4
5. This programmable core clock capability is useful for
, and V
illustrates typical system clock ratios.
Table 9
DDMEM
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Divider Ratio
VCO/SCLK
2:1
6:1
10:1
Page
for details. The maximal system clock rate
voltages (see
65), it also depends on the applied V
Table 6
Example Frequency Ratios
(MHz)
VCO
300
300
400
200
Example Frequency Ratios
(MHz)
VCO
100
300
400
provide a number of mecha-
Table 11 on Page
SCLK
. The SSEL value can be
CCLK
300
150
100
25
SCLK
50
50
40
Table
Rev. B | Page 14 of 68 | January 2011
21).
6) for
DDINT
DDINT
,
bits of the reset configuration register, sampled during power-
on resets and software-initiated resets, implement the modes
shown in
Table 6. Booting Modes
BMODE2–0 Description
000
001
010
011
100
101
110
111
• Idle/no boot mode (BMODE = 0x0)—In this mode, the
• Boot from 8-bit or 16-bit external flash memory
• Boot from internal SPI memory (BMODE = 0x2)—The
• Boot from external SPI EEPROM or flash
• Boot from SPI0 host device (BMODE = 0x4)—The proces-
processor goes into idle. The idle boot mode helps recover
from illegal operating modes, such as when the user has
mis configured the OTP memory.
(BMODE = 0x1)—In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and—depend-
ing on instructions containing in the header—the boot
kernel performs 8-bit or 16-bit boot or starts program exe-
cution at the address provided by the header. By default, all
configuration settings are set for the slowest device possible
(3-cycle hold time, 15-cycle R/W access times, 4-cycle
setup).
The ARDY is not enabled by default, but it can be enabled
by OTP programming. Similarly, all interface behavior and
timings can be customized by OTP programming. This
includes activation of burst-mode or page-mode operation.
In this mode, all signals belonging to the asynchronous
interface are enabled at the port muxing level.
processor uses the internal PH8 GPIO signal to load code
previously loaded to the 4 Mbit internal SPI flash con-
nected to SPI0. Only available on the ADSP-BF512F/
ADSP-BF514F/ADSP-BF516F/ADSP-BF518F.
(BMODE = 0x3)—8-bit, 16-bit, 24-bit or 32-bit address-
able devices are supported. The processor uses the PG15
GPIO signal (at SPI0SEL2) to select a single SPI
EEPROM/flash device connected to the SPI0 interface;
then submits a read command and successive address bytes
(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device
is detected. Pull-up resistors are required on the SSEL and
MISO signals. By default, a value of 0x85 is written to the
SPI0_BAUD register.
sor operates in SPI slave mode and is configured to receive
the bytes of the LDR file from an SPI host (master) agent.
In the host, the HWAIT signal must be interrogated by the
Table
Idle - No boot
Boot from 8- or 16-bit external flash memory
Boot from internal SPI memory
Boot from external SPI memory (EEPROM or flash)
Boot from SPI0 host
Boot from OTP memory
Boot from SDRAM
Boot from UART0 Host
6.