ADSP-BF512KSWZ-3 Analog Devices Inc, ADSP-BF512KSWZ-3 Datasheet - Page 37

• Manufacturer Part Number: ADSP-BF512KSWZ-3
• Description: Low-Power Blackfin Processor
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF512KSWZ-3

• Interface: I²C, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Ports
Table 33
through
Table 33. Serial Ports—External Clock
1
2
3
Table 34. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Verified in design but untested.
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
SUDTE
SUDRE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
1
2
1
1
1
2
2
1
1
3
3
3
1
2
2
2
3
Figure 24 on Page 40
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
through
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
Start-Up Delay From SPORT Enable To First External TFSx
Start-Up Delay From SPORT Enable To First External RFSx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TSCLKx/RSCLKx Width
Table 36 on Page 40
describe serial port operations.
and
Figure 21 on Page 38
Rev. B | Page 37 of 68 | January 2011
Min
−2
−1.8
10
11
–1.5
11
–1.5
Min
3
3
3
3.5
7
2 × t
4 × t
4 × t
0
0
SCLK
SCLKE
SCLKE
1.8V Nominal
1.8V Nominal
V
V
DDEXT
DDEXT
Max
3
3
Max
10
10
Min
9.6
–1.5
9.6
–1.5
−1
−1.5
8
Min
3
3
3
3
4.5
2 × t
4 × t
4 × t
0
0
2.5 V/3.3V Nominal
2.5 V/3.3V Nominal
SCLK
SCLKE
SCLKE
V
V
DDEXT
DDEXT
Max
3
3
Max
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns